Inventor · disambiguated record
Vishwas M. Rao
Also filed as: RAO VISHWAS · RAO VISHWAS M
18 granted patents·4 pending applications·93 citations·filing 2006–2014
93Inventor score
Top patents by PatentIndex Score
22 records- 0189US8024694B2Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristicsAGERE SYSTEMS INC·Filed 2009·Granted Sep 20, 2011·10 cites·7 claims
- 0285US8307324B2Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristicsJAMANN JOSEPH J·Filed 2011·Granted Nov 6, 2012·6 cites·6 claims
- 0384US8341573B2Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flowRAO VISHWAS M·Filed 2010·Granted Dec 25, 2012·8 cites·7 claims
- 0484US8281266B2Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed therebyJAMANN JOSEPH J·Filed 2009·Granted Oct 2, 2012·8 cites·15 claims
- 0583US7930674B2Modifying integrated circuit designs to achieve multiple operating frequency targetsAGERE SYSTEMS INC·Filed 2007·Granted Apr 19, 2011·14 cites·21 claims
- 0682US8543951B2Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flowLSI CORP·Filed 2012·Granted Sep 24, 2013·6 cites·18 claims
- 0782US8239805B2Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the methodRAO VISHWAS M·Filed 2009·Granted Aug 7, 2012·9 cites·10 claims
- 0881US8539419B2Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the methodRAO VISHWAS M·Filed 2012·Granted Sep 17, 2013·5 cites·9 claims
- 0973US7424693B2Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pinsAGERE SYSTEMS INC·Filed 2006·Granted Sep 9, 2008·8 cites·11 claims
- 1070US8539423B2Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristicsAGERE SYSTEMS LLC·Filed 2012·Granted Sep 17, 2013·1 cites·10 claims
- 1168US8127264B2Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methodsPARKER JAMES C·Filed 2009·Granted Feb 28, 2012·7 cites·20 claims
- 1267US8122422B2Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus thereforRAO VISHWAS M·Filed 2009·Granted Feb 21, 2012·6 cites·20 claims
- 1363US8522179B1System and method for managing timing margin in a hierarchical integrated circuit design processGRIESBACH WILLIAM R·Filed 2012·Granted Aug 27, 2013·2 cites·20 claims
- 1461US8689161B2Methods for designing integrated circuits employing pre-determined timing-realizable clock-insertion delays and integrated circuit design toolsRAO VISHWAS M·Filed 2010·Granted Apr 1, 2014·1 cites·20 claims
- 1558US7610568B2Methods and apparatus for making placement sensitive logic modificationsAGERE SYSTEMS INC·Filed 2006·Granted Oct 27, 2009·2 cites·20 claims
- 1658US2014298277A1Methods for designing integrated circuits employing voltage scaling and integrated circuits designed therebyAGERE SYSTEMS LLC·Filed 2014·Application pending·0 cites
- 1755US8683407B2Hierarchical design flow generatorLSI CORP·Filed 2013·Granted Mar 25, 2014·0 cites·20 claims
- 1853US8806408B2Methods for designing integrated circuits employing voltage scaling and integrated circuits designed therebyPARKER JAMES C·Filed 2009·Granted Aug 12, 2014·0 cites·20 claims
- 1948US2013055175A1Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed therebyJAMANN JOSEPH J·Filed 2012·Application pending·0 cites
- 2045US2014337598A1Modulation of flash programming based on host activityLSI CORP·Filed 2013·Application pending·0 cites
- 2142US8468478B2Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pinsALTER STEPHANIE L·Filed 2008·Granted Jun 18, 2013·0 cites·21 claims
- 2241US2014059505A1Method for designing integrated circuits employing correct-by-construction progressive modeling and an apparatus employing the methodBLAIR GERARD M·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →