Inventor · disambiguated record
Deepak Mathew
Also filed as: MATHEW DEEPAK · MATHEW DEEPAK MOLLY
19 granted patents·11 pending applications·100 citations·filing 2000–2023
91Inventor score
Top patents by PatentIndex Score
30 records- 0189US6735180B1Method of sending feedback information in a fast automatic repeat request forming part of an overall wireless communication systemNOKIA MOBILE PHONES LTD·Filed 2000·Granted May 11, 2004·60 cites·17 claims
- 0281USRE42744EMethod of sending feedback information in a fast automatic repeat request forming part of an overall wireless communication systemNOKIA CORP·Filed 2005·Granted Sep 27, 2011·8 cites·50 claims
- 0377US9363749B2Dynamic power scaling of digital modemsQUALCOMM INC·Filed 2013·Granted Jun 7, 2016·4 cites·22 claims
- 0476US11900111B2Permutation instructionQUALCOMM INC·Filed 2021·Granted Feb 13, 2024·1 cites·30 claims
- 0571US7336699B2Method and apparatus for code identification in wireless applicationsANALOG DEVICES INC·Filed 2003·Granted Feb 26, 2008·13 cites·29 claims
- 0664US7277474B2Finger allocation for a path searcher in a multipath receiverANALOG DEVICES INC·Filed 2003·Granted Oct 2, 2007·8 cites·25 claims
- 0763US8358988B2Interface between chip rate processing and bit rate processing in wireless downlink receiverMEDIATEK INC·Filed 2006·Granted Jan 22, 2013·3 cites·27 claims
- 0862US9342479B2Systems and methods of data extraction in a vector processorFRIDMAN JOSE·Filed 2012·Granted May 17, 2016·2 cites·26 claims
- 0957US12159140B2Instruction set architecture for neural network quantization and packingQUALCOMM INC·Filed 2022·Granted Dec 3, 2024·0 cites·12 claims
- 1054US8358987B2Re-quantization in downlink receiver bit rate processorMEDIATEK INC·Filed 2006·Granted Jan 22, 2013·1 cites·24 claims
- 1154US2024104356A1Quantized neural network architectureQUALCOMM INC·Filed 2022·Application pending·0 cites
- 1251US8054922B2Parameter estimation for modulated signalsMEDIATEK INC·Filed 2008·Granted Nov 8, 2011·0 cites·34 claims
- 1349US2025168857A1Pdcch monitoring skipping at coreset levelQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1447US9130786B2Device and method for computing a channel estimateQUALCOMM INC·Filed 2013·Granted Sep 8, 2015·0 cites·26 claims
- 1547US2023351144A1Instruction Set Architecture for Implementing Linear Activation Functions in Neural NetworksQUALCOMM INC·Filed 2022·Application pending·0 cites
- 1647US2023350640A1System and method of rotating vector inputQUALCOMM INC·Filed 2022·Application pending·0 cites
- 1746US9268571B2Selective coupling of an address line to an element bank of a vector register fileQUALCOMM INC·Filed 2012·Granted Feb 23, 2016·0 cites·33 claims
- 1845US2015052330A1Vector arithmetic reductionQUALCOMM INC·Filed 2013·Application pending·0 cites
- 1945US2014281368A1Cycle sliced vectors and slot execution on a shared datapathQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2044US2009081973A1Multi-slot power control for wireless transmissionANALOG DEVICES INC·Filed 2007·Application pending·0 cites
- 2143US10466967B2System and method for piecewise linear approximationQUALCOMM INC·Filed 2016·Granted Nov 5, 2019·0 cites·30 claims
- 2243US2023097103A1Fast fourier transform using phasor tableQUALCOMM INC·Filed 2021·Application pending·0 cites
- 2341US10638346B2Channel state computation for enhanced carrier aggregationQUALCOMM INC·Filed 2016·Granted Apr 28, 2020·0 cites·20 claims
- 2441US8149702B2Multi-mode bit rate processorMATHEW DEEPAK·Filed 2008·Granted Apr 3, 2012·0 cites·37 claims
- 2541US2008080542A1Architecture for downlink receiver bit rate processorANALOG DEVICES INC·Filed 2006·Application pending·0 cites
- 2640US2008080444A1Transport channel buffer organization in downlink receiver bit rate processorANALOG DEVICES INC·Filed 2006·Application pending·0 cites
- 2736US8316378B2Data flow control in wireless communication systemsSHEN JOHN ZIJUN·Filed 2008·Granted Nov 20, 2012·0 cites·22 claims
- 2835US2009161647A1Td-scdma uplink processingMESTECHKIN RUSS·Filed 2008·Application pending·0 cites
- 2934US10622054B2Using runtime reverse engineering to optimize DRAM refreshTU KAISERSLAUTERN·Filed 2018·Granted Apr 14, 2020·0 cites·19 claims
- 3021US8094641B2TD-SCDMA uplink processingMATHEW DEEPAK·Filed 2008·Granted Jan 10, 2012·0 cites·49 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →