Inventor · disambiguated record
Rob A. Rutenbar
Also filed as: RUTENBAR ROB · RUTENBAR ROB A
12 granted patents·1 pending application·178 citations·filing 2002–2009
92Inventor score
Files withCADENCE DESIGN SYSTEMS INC5SINGHEE AMITH2UNIV CARNEGIE MELLON2BOURKE PATRICK J1LIN EDWARD1
Top patents by PatentIndex Score
13 records- 0189US8352265B1Hardware implemented backend search engine for a high-rate speech recognition systemLIN EDWARD·Filed 2008·Granted Jan 8, 2013·31 cites·24 claims
- 0287US8155938B2Method and apparatus for sampling and predicting rare events in complex electronic devices, circuits and systemsSINGHEE AMITH·Filed 2008·Granted Apr 10, 2012·22 cites·15 claims
- 0376US8290761B1Method and apparatus for rapidly modeling and simulating intra-die statistical variations in integrated circuits using compressed parameter modelsSINGHEE AMITH·Filed 2009·Granted Oct 16, 2012·9 cites·26 claims
- 0473US8463610B1Hardware-implemented scalable modular engine for low-power speech recognitionBOURKE PATRICK J·Filed 2009·Granted Jun 11, 2013·19 cites·20 claims
- 0573US7093220B2Method for generating constrained component placement for integrated circuits and packagesCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 15, 2006·19 cites·38 claims
- 0670US7058916B2Method for automatically sizing and biasing circuits by means of a databaseCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jun 6, 2006·19 cites·43 claims
- 0769US8639510B1Acoustic scoring unit implemented on a single FPGA or ASICYU KAI·Filed 2008·Granted Jan 28, 2014·6 cites·12 claims
- 0869US7920992B2Method and system for modeling uncertainties in integrated circuits, systems, and fabrication processesUNIV CARNEGIE MELLON·Filed 2006·Granted Apr 5, 2011·7 cites·24 claims
- 0968US6957400B2Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit designCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Oct 18, 2005·15 cites·39 claims
- 1068US6874133B2Integrated circuit design layout compaction methodCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Mar 29, 2005·14 cites·13 claims
- 1159US6918102B2Method and apparatus for exact relative positioning of devices in a semiconductor circuit layoutCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jul 12, 2005·7 cites·22 claims
- 1255US6711725B1Method of creating conformal outlines for use in transistor level semiconductor layoutsNEOLINEAR INC·Filed 2002·Granted Mar 23, 2004·10 cites·19 claims
- 1347US2009248370A1Method and Apparatus for Applying "Quasi-Monte Carlo" Methods to Complex Electronic Devices Circuits and SystemsUNIV CARNEGIE MELLON·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →