Inventor · disambiguated record
Yoshiyuki Haraguchi
Also filed as: HARAGUCHI YOSHIYUKI
11 granted patents·2 pending applications·209 citations·filing 1993–2003
92Inventor score
Top patents by PatentIndex Score
13 records- 0177US5384741ASemiconductor memory device adapted for preventing a test mode operation from undesirably occurringMITSUBISHI ELECTRIC CORP·Filed 1994·Granted Jan 24, 1995·35 cites·12 claims
- 0277US5305267ASemiconductor memory device adapted for preventing a test mode operation from undesirably occurringMITSUBISHI ELECTRIC CORP·Filed 1993·Granted Apr 19, 1994·36 cites·10 claims
- 0376US6178127B1Semiconductor memory device allowing reliable repairing of a defective columnMITSUBISHI ELECTRIC CORP·Filed 2000·Granted Jan 23, 2001·25 cites·9 claims
- 0472US6859079B2Semiconductor device capable of accurately producing internal multi-phase clock signalRENESAS TECH CORP·Filed 2003·Granted Feb 22, 2005·20 cites·10 claims
- 0561US5446692ASemiconductor memory device having redundancy memory cells shared among memory blocksMITSUBISHI ELECTRIC CORP·Filed 1993·Granted Aug 29, 1995·22 cites·3 claims
- 0659US5469391ASemiconductor memory device including redundancy circuit for remedying defect in memory portionMITSUBISHI ELECTRIC CORP·Filed 1994·Granted Nov 21, 1995·19 cites·11 claims
- 0757US5677889AStatic type semiconductor device operable at a low voltage with small power consumptionMITSUBISHI ELECTRIC CORP·Filed 1995·Granted Oct 14, 1997·17 cites·10 claims
- 0856US6862680B2Microprocessor processing specified instructions as operandsRENESAS TECH CORP·Filed 2001·Granted Mar 1, 2005·5 cites·5 claims
- 0956US5850367AStatic type semiconductor memory with latch circuit amplifying read data read on a sub bit line pair and transferring the amplified read data to a main bit line pair and operation method thereofMITSUBISHI ELECTRIC CORP·Filed 1997·Granted Dec 15, 1998·17 cites·8 claims
- 1047US6754865B2Integrated circuitRENESAS TECHNOLOGYY CORP·Filed 2000·Granted Jun 22, 2004·8 cites·9 claims
- 1137US5650978ASemiconductor memory device having data transition detecting functionMITSUBISHI ELECTRIC CORP·Filed 1995·Granted Jul 22, 1997·5 cites·8 claims
- 1235US2004157576A1Communication device performing communication using two clock signals complementary to each otherRENESAS TECH CORP·Filed 2003·Application pending·0 cites
- 1335US2003098506A1Semiconductor device having a semiconductor chip and a lead substrate connected with each other through pads and patterned lead wires without short-circuiting the padsFiled 2002·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Yoshiyuki Haraguchi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →