Inventor · disambiguated record
Dominique D'Inverno
Also filed as: D INVERNO DOMINIQUE · D INVERNO DOMINIQUE BENOIT · D INVERNO DOMINIQUE BENOIT JAC · D INVERNO DOMINIQUE BENOIT JACQUES
41 granted patents·8 pending applications·1,242 citations·filing 1998–2007
98Inventor score
Top patents by PatentIndex Score
49 records- 0196US7111177B1System and method for executing tasks according to a selected scenario in response to probabilistic power consumption information of each scenarioTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 19, 2006·139 cites·24 claims
- 0294US7174194B2Temperature field controlled scheduling for processing systemsTEXAS INSTRUMENTS INC·Filed 2001·Granted Feb 6, 2007·104 cites·15 claims
- 0394US6901521B2Dynamic hardware control for energy management systems using task attributesTEXAS INSTRUMENTS INC·Filed 2001·Granted May 31, 2005·99 cites·12 claims
- 0492US7062304B2Task based adaptative profiling and debuggingTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 13, 2006·77 cites·20 claims
- 0592US6889330B2Dynamic hardware configuration for energy management systems using task attributesTEXAS INSTRUMENTS INC·Filed 2001·Granted May 3, 2005·76 cites·14 claims
- 0690US7146613B2JAVA DSP acceleration by byte-code optimizationTEXAS INSTRUMENTS INC·Filed 2002·Granted Dec 5, 2006·65 cites·10 claims
- 0790US6751706B2Multiple microprocessors with a shared cacheTEXAS INSTRUMENTS INC·Filed 2001·Granted Jun 15, 2004·65 cites·13 claims
- 0889US6681297B2Software controlled cache configuration based on average miss rateTEXAS INSTRUMENTS INC·Filed 2001·Granted Jan 20, 2004·55 cites·13 claims
- 0986US7509391B1Unified memory management system for multi processor heterogeneous architectureTEXAS INSTRUMENTS INC·Filed 1999·Granted Mar 24, 2009·119 cites·17 claims
- 1085US6826652B1Smart cacheTEXAS INSTRUMENTS INC·Filed 2000·Granted Nov 30, 2004·41 cites·15 claims
- 1184US7120715B2Priority arbitration based on current task and MMUTEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 10, 2006·37 cites·16 claims
- 1284US6742104B2Master/slave processing system with shared translation lookaside bufferTEXAS INSTRUMENTS INC·Filed 2001·Granted May 25, 2004·42 cites·28 claims
- 1378US6760829B2MMU descriptor having big/little endian bit to control the transfer data between devicesTEXAS INSTRUMENTS INC·Filed 2001·Granted Jul 6, 2004·24 cites·11 claims
- 1476US6772326B2Interruptible and re-entrant cache clean range instructionTEXAS INSTRUMENTS INC·Filed 2002·Granted Aug 3, 2004·22 cites·19 claims
- 1574US7069415B2System and method to automatically stack and unstack Java local variablesTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 27, 2006·19 cites·15 claims
- 1674US6792508B1Cache with multiple fill modesTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 14, 2004·19 cites·24 claims
- 1772US7716673B2Tasks distribution in a multi-processor including a translation lookaside buffer shared between processorsTEXAS INSTRUMENTS INC·Filed 2003·Granted May 11, 2010·16 cites·15 claims
- 1872US6412048B1Traffic controller using priority and burst control for reducing access latencyTEXAS INSTRUMENTS INC·Filed 1998·Granted Jun 25, 2002·47 cites·13 claims
- 1969US6253297B1Memory control using memory state information for reducing access latencyTEXAS INSTRUMENTS INC·Filed 1998·Granted Jun 26, 2001·43 cites·24 claims
- 2068US6742103B2Processing system with shared translation lookaside bufferTEXAS INSTRUMENTS INC·Filed 2001·Granted May 25, 2004·13 cites·34 claims
- 2165US6769052B2Cache with selective write allocationTEXAS INSTRUMENTS INC·Filed 2002·Granted Jul 27, 2004·14 cites·11 claims
- 2264US8032891B2Energy-aware scheduling of application executionTEXAS INSTRUMENTS INC·Filed 2002·Granted Oct 4, 2011·14 cites·20 claims
- 2364US7434021B2Memory allocation in a multi-processor systemTEXAS INSTRUMENTS INC·Filed 2004·Granted Oct 7, 2008·10 cites·16 claims
- 2464US6934820B2Traffic controller using priority and burst control for reducing access latencyTEXAS INSTRUMENTS INC·Filed 2002·Granted Aug 23, 2005·7 cites·20 claims
- 2562US8539159B2Dirty cache line write back policy based on stack size trend informationCHAUVEL GERARD·Filed 2003·Granted Sep 17, 2013·8 cites·4 claims
- 2660US7941790B2Data processing apparatus, system and methodTEXAS INSTRUMENTS INC·Filed 2001·Granted May 10, 2011·9 cites·22 claims
- 2759US8190861B2Micro-sequence based security modelCHAUVEL GERARD·Filed 2007·Granted May 29, 2012·1 cites·26 claims
- 2859US7634643B2Stack register reference control bit in source operand of instructionTEXAS INSTRUMENTS INC·Filed 2003·Granted Dec 15, 2009·6 cites·14 claims
- 2958US7330937B2Management of stack-based memory usage in a processorTEXAS INSTRUMENTS INC·Filed 2004·Granted Feb 12, 2008·6 cites·34 claims
- 3055US7496930B2Accessing device driver memory in programming language representationTEXAS INSTRUMENTS INC·Filed 2004·Granted Feb 24, 2009·4 cites·26 claims
- 3153US7565385B2Embedded garbage collectionTEXAS INSTRUMENTS INC·Filed 2004·Granted Jul 21, 2009·3 cites·11 claims
- 3253US7543014B2Saturated arithmetic in a processing unitTEXAS INSTRUMENTS INC·Filed 2003·Granted Jun 2, 2009·2 cites·17 claims
- 3352US6996683B2Cache coherency in a multi-processor systemTEXAS INSTRUMENTS INC·Filed 2003·Granted Feb 7, 2006·2 cites·13 claims
- 3447US7386671B2Smart cacheTEXAS INSTRUMENTS INC·Filed 2004·Granted Jun 10, 2008·0 cites·11 claims
- 3545US7840784B2Test and skip processor instruction having at least one register operandTEXAS INSTRUMENTS INC·Filed 2003·Granted Nov 23, 2010·0 cites·25 claims
- 3645US7840782B2Mixed stack-based RISC processorTEXAS INSTRUMENTS INC·Filed 2003·Granted Nov 23, 2010·0 cites·38 claims
- 3745US7203797B2Memory management of local variablesTEXAS INSTRUMENTS INC·Filed 2003·Granted Apr 10, 2007·0 cites·15 claims
- 3844US8429383B2Multi-processor computing system having a JAVA stack machine and a RISC-based processorCHAUVEL GERARD·Filed 2003·Granted Apr 23, 2013·0 cites·14 claims
- 3944US2004024969A1Methods and apparatuses for managing memoryTEXAS INSTRUMENTS INC·Filed 2003·Application pending·0 cites
- 4044US2004024999A1Micro-sequence execution in a processorTEXAS INSTRUMENTS INC·Filed 2003·Application pending·0 cites
- 4144US2005033945A1Dynamically changing the semantic of an instructionFiled 2004·Application pending·0 cites
- 4244US2004024990A1Processor that accommodates multiple instruction sets and multiple decode modesTEXAS INSTRUMENTS INC·Filed 2003·Application pending·0 cites
- 4344US2004260911A1Unresolved instruction resolutionFiled 2004·Application pending·0 cites
- 4444US2004024970A1Methods and apparatuses for managing memoryTEXAS INSTRUMENTS INC·Filed 2003·Application pending·0 cites
- 4541US6430664B1Digital signal processor with direct and virtual addressingTEXAS INSTRUMENTS INC·Filed 1999·Granted Aug 6, 2002·12 cites·22 claims
- 4641US6321299B1Computer circuits, systems, and methods using partial cache cleaningTEXAS INSTRUMENTS INC·Filed 1998·Granted Nov 20, 2001·13 cites·29 claims
- 4741US2004010785A1Application execution profiling in conjunction with a virtual machineFiled 2002·Application pending·0 cites
- 4841US2002069341A1Multilevel cache architecture and data transferFiled 2001·Application pending·0 cites
- 4937US6606687B1Optimized hardware cleaning function for VIVT data cacheTEXAS INSTRUMENTS INC·Filed 1999·Granted Aug 12, 2003·9 cites·4 claims
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