Inventor · disambiguated record
Wen-Chun Chiu
Also filed as: CHIU WEN CHUN
5 granted patents·6 pending applications·13 citations·filing 2007–2024
71Inventor score
Top patents by PatentIndex Score
11 records- 0182US8093104B1Multi-chip stacking method to reduce voids between stacked chipsLEE KUO-YUAN·Filed 2011·Granted Jan 10, 2012·9 cites·17 claims
- 0262US7677945B2Method of forming an external electrode fluorescent lamp, thick film electrode compositions used therein, and lamps and LCD devices formed thereofDU PONT·Filed 2007·Granted Mar 16, 2010·2 cites·9 claims
- 0358US2025062050A1Superconductor-metal Conductive Material and the Electronic Component and the Method Using the SameUBRIGHT OPTRONICS CORP·Filed 2024·Application pending·0 cites
- 0457US8361841B2Mold array process method to encapsulate substrate cut edgesWALTON ADVANCED ENG INC·Filed 2011·Granted Jan 29, 2013·1 cites·14 claims
- 0556US8815645B2Multi-chip stacking method to reduce voids between stacked chipsLEE KUO-YUAN·Filed 2011·Granted Aug 26, 2014·1 cites·15 claims
- 0643US7969083B2Discharge lamp and production method thereofWELLYPOWER OPTRONICS CORP·Filed 2009·Granted Jun 28, 2011·0 cites·23 claims
- 0743US2010219521A1Window type semiconductor packageLEE KUO-YUAN·Filed 2009·Application pending·0 cites
- 0840US2013146806A1Porous lithium phosphate metal salt and method for preparing the sameCHIU WEN CHUN·Filed 2012·Application pending·0 cites
- 0936US2009294792A1Card type memory packageWALTON ADVANCED ENG INC·Filed 2008·Application pending·0 cites
- 1034US2012077312A1Flip-chip bonding method to reduce voids in underfill materialLEE KUO-YUAN·Filed 2011·Application pending·0 cites
- 1134US2012264257A1Mold array process method to prevent exposure of substrate peripheriesLEE KUO-YUAN·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →