Inventor · disambiguated record
Kelvin D. Goveas
Also filed as: GOVEAS KELVIN · GOVEAS KELVIN D · GOVEAS KELVIN DOMNIC
16 granted patents·3 pending applications·290 citations·filing 1995–2023
92Inventor score
Files withADVANCED MICRO DEVICES INC11ADVANCED RISC MACH LTD3AZIMUTH TECH LLC1FLEISCHMAN JAY E1GOVEAS KELVIN1
Top patents by PatentIndex Score
19 records- 0192US7464255B1Using a shuffle unit to implement shift operations in a processorADVANCED MICRO DEVICES INC·Filed 2005·Granted Dec 9, 2008·38 cites·17 claims
- 0284US5748516AFloating point processing unit with forced arithmetic resultsADVANCED MICRO DEVICES INC·Filed 1995·Granted May 5, 1998·121 cites·17 claims
- 0383US7284117B1Processor that predicts floating point instruction latency based on predicted precisionADVANCED MICRO DEVICES INC·Filed 2003·Granted Oct 16, 2007·39 cites·24 claims
- 0475US7565513B2Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operationsADVANCED MICRO DEVICES INC·Filed 2007·Granted Jul 21, 2009·7 cites·20 claims
- 0570US8407271B2Method for floating point round to integer operationHURD KEVIN·Filed 2009·Granted Mar 26, 2013·7 cites·20 claims
- 0665US12481310B2Method and apparatus for deskewing die to die communication between system on chip devicesVENTANA MICRO SYSTEMS INC·Filed 2023·Granted Nov 25, 2025·0 cites·20 claims
- 0760US7028068B1Alternate phase dual compression-tree multiplierADVANCED MICRO DEVICES INC·Filed 2003·Granted Apr 11, 2006·7 cites·23 claims
- 0858US5761105AReservation station including addressable constant store for a floating point processing unitADVANCED MICRO DEVICES INC·Filed 1997·Granted Jun 2, 1998·34 cites·13 claims
- 0950US9959122B2Single cycle instruction pipeline schedulingADVANCED MICRO DEVICES INC·Filed 2013·Granted May 1, 2018·0 cites·20 claims
- 1048US11392378B2Executing a set of load operations for a gather-load instruction and controlling handling of another instruction that depends on completion of the gather-load instructionADVANCED RISC MACH LTD·Filed 2019·Granted Jul 19, 2022·0 cites·17 claims
- 1148US9317250B2Floating point multiply-add unit with denormal number supportADVANCED MICRO DEVICES INC·Filed 2012·Granted Apr 19, 2016·0 cites·20 claims
- 1248US5878266AReservation station for a floating point processing unitADVANCED MICRO DEVICES INC·Filed 1995·Granted Mar 2, 1999·20 cites·36 claims
- 1348US2023037780A1Computing device with one or more hardware accelerators directly coupled with cluster of processorsAZIMUTH TECH LLC·Filed 2022·Application pending·0 cites
- 1447US6122721AReservation station for a floating point processing unitADVANCED MICRO DEVICES INC·Filed 1999·Granted Sep 19, 2000·17 cites·39 claims
- 1544US11327791B2Apparatus and method for operating an issue queueADVANCED RISC MACH LTD·Filed 2019·Granted May 10, 2022·0 cites·20 claims
- 1644US2008209185A1Processor with reconfigurable floating point unitADVANCED MICRO DEVICES INC·Filed 2007·Application pending·0 cites
- 1741US10310809B2Apparatus and method for supporting a conversion instructionADVANCED RISC MACH LTD·Filed 2016·Granted Jun 4, 2019·0 cites·13 claims
- 1836US9110802B2Processor and method implemented by a processor to implement mask load and store instructionsGOVEAS KELVIN·Filed 2010·Granted Aug 18, 2015·0 cites·27 claims
- 1932US2012191952A1Processor implementing scalar code optimizationFLEISCHMAN JAY E·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →