Inventor · disambiguated record
Jose L. Neves
Also filed as: NEVES JOSE · NEVES JOSE L · NEVES JOSE L P · NEVES JOSE LUIS
37 granted patents·1 pending application·335 citations·filing 1999–2019
97Inventor score
Top patents by PatentIndex Score
38 records- 0187US6401234B1Method and system for re-routing interconnects within an integrated circuit design having blockages and baysIBM·Filed 1999·Granted Jun 4, 2002·132 cites·21 claims
- 0282US8640075B2Early design cycle optimzationALPERT CHARLES JAY·Filed 2012·Granted Jan 28, 2014·6 cites·19 claims
- 0381US7376924B2Methods for placement which maintain optimized behavior, while improving wireability potentialIBM·Filed 2005·Granted May 20, 2008·10 cites·8 claims
- 0481US6651230B2Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit designIBM·Filed 2001·Granted Nov 18, 2003·31 cites·21 claims
- 0579US7356793B2Genie: a method for classification and graphical display of negative slack timing test failuresIBM·Filed 2005·Granted Apr 8, 2008·9 cites·17 claims
- 0679US6523159B2Method for adding decoupling capacitance during integrated circuit designIBM·Filed 2001·Granted Feb 18, 2003·29 cites·52 claims
- 0776US9934341B2Simulation of modifications to microprocessor designIBM·Filed 2015·Granted Apr 3, 2018·2 cites·10 claims
- 0876US6490708B2Method of integrated circuit design by selection of noise tolerant gatesIBM·Filed 2001·Granted Dec 3, 2002·24 cites·32 claims
- 0975US7921398B2System and medium for placement which maintain optimized timing behavior, while improving wireability potentialIBM·Filed 2008·Granted Apr 5, 2011·6 cites·8 claims
- 1075US7810062B2Method for eliminating negative slack in a netlist via transformation and slack categorizationIBM·Filed 2007·Granted Oct 5, 2010·7 cites·11 claims
- 1174US9038009B2Early design cycle optimizationIBM·Filed 2013·Granted May 19, 2015·3 cites·9 claims
- 1273US11176301B2Noise impact on function (NIOF) reduction for integrated circuit designIBM·Filed 2019·Granted Nov 16, 2021·1 cites·20 claims
- 1372US10831938B1Parallel power down processing of integrated circuit designIBM·Filed 2019·Granted Nov 10, 2020·1 cites·17 claims
- 1471US10885243B1Logic partition reporting for integrated circuit designIBM·Filed 2019·Granted Jan 5, 2021·1 cites·17 claims
- 1571US10831953B1Logic partition identifiers for integrated circuit designIBM·Filed 2019·Granted Nov 10, 2020·1 cites·20 claims
- 1671US6560752B1Apparatus and method for buffer library selection for use in buffer insertionIBM·Filed 2000·Granted May 6, 2003·16 cites·47 claims
- 1770US11650987B2Query response using semantically similar database recordsIBM·Filed 2019·Granted May 16, 2023·1 cites·19 claims
- 1869US10878152B1Single-bit latch optimization for integrated circuit (IC) designIBM·Filed 2019·Granted Dec 29, 2020·1 cites·20 claims
- 1969US7823108B2Chip having timing analysis of paths performed within the chip during the design processIBM·Filed 2007·Granted Oct 26, 2010·5 cites·17 claims
- 2069US7047506B2Method to identify geometrically non-overlapping optimization partitions for parallel timing closureIBM·Filed 2003·Granted May 16, 2006·15 cites·21 claims
- 2168US6799309B2Method for optimizing a VLSI floor planner using a path based hyper-edge representationIBM·Filed 2002·Granted Sep 28, 2004·17 cites·9 claims
- 2267US7895539B2System for improving a logic circuit and associated methodsIBM·Filed 2007·Granted Feb 22, 2011·5 cites·17 claims
- 2366US9858383B2Incremental parasitic extraction for coupled timing and power optimizationIBM·Filed 2015·Granted Jan 2, 2018·1 cites·20 claims
- 2466US8006213B2Optimization method of integrated circuit design for reduction of global clock load and balancing clock skewIBM·Filed 2008·Granted Aug 23, 2011·4 cites·13 claims
- 2566US7831946B2Clock distribution network wiring structureIBM·Filed 2007·Granted Nov 9, 2010·5 cites·19 claims
- 2663US9223918B2Reducing repeater powerKARTSCHOKE PAUL D·Filed 2012·Granted Dec 29, 2015·2 cites·14 claims
- 2757US11030376B2Net routing for integrated circuit (IC) designIBM·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
- 2854US9256705B2Reducing repeater powerIBM·Filed 2013·Granted Feb 9, 2016·0 cites·6 claims
- 2953US10169526B2Incremental parasitic extraction for coupled timing and power optimizationIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 3053US9928322B2Simulation of modifications to microprocessor designIBM·Filed 2016·Granted Mar 27, 2018·0 cites·18 claims
- 3152US9734270B2Control path power adjustment for chip designIBM·Filed 2015·Granted Aug 15, 2017·0 cites·8 claims
- 3250US10831966B1Multi-fanout latch placement optimization for integrated circuit (IC) designIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 3350US9703910B2Control path power adjustment for chip designIBM·Filed 2015·Granted Jul 11, 2017·0 cites·12 claims
- 3449US11410031B2Dynamic updating of a word embedding modelIBM·Filed 2018·Granted Aug 9, 2022·0 cites·25 claims
- 3548US7979838B2Method of automating creation of a clock control distribution network in an integrated circuit floorplanIBM·Filed 2008·Granted Jul 12, 2011·0 cites·12 claims
- 3646US2008052655A1Chip Having Timing Analysis of Paths Performed Within the Chip During the Design ProcessIBM·Filed 2007·Application pending·0 cites
- 3737US10331840B2Resource aware method for optimizing wires for slew, slack, or noiseIBM·Filed 2016·Granted Jun 25, 2019·0 cites·19 claims
- 3834US8108821B2Reduction of logic and delay through latch polarity inversionCHEN JONATHAN Y·Filed 2010·Granted Jan 31, 2012·0 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →