Inventor · disambiguated record
Thomas Rupp
Also filed as: RUPP THOMAS · RUPP THOMAS S · RUPP THOMAS STEFFEN
18 granted patents·2 pending applications·367 citations·filing 1998–2023
95Inventor score
Files withIBM7INFINEON TECHNOLOGIES AG4INFINEON TECHNOLOGIES CORP4SIEMENS AG3INFINEON TECHNOLOGIES AUSTRIA AG1
Top patents by PatentIndex Score
20 records- 0192US6258659B1Embedded vertical DRAM cells and dual workfunction logic gatesIBM·Filed 2000·Granted Jul 10, 2001·56 cites·6 claims
- 0287US6172390B1Semiconductor device with vertical transistor and buried word lineSIEMENS AG·Filed 1998·Granted Jan 9, 2001·56 cites·15 claims
- 0382US6153902AVertical DRAM cell with wordline self-aligned to storage trenchIBM·Filed 1999·Granted Nov 28, 2000·37 cites·15 claims
- 0482US6091094AVertical device formed adjacent to a wordline sidewall and method for semiconductor chipsSIEMENS AG·Filed 1998·Granted Jul 18, 2000·46 cites·17 claims
- 0579US6291335B1Locally folded split level bitline wiringINFINEON TECHNOLOGIES AG·Filed 1999·Granted Sep 18, 2001·47 cites·22 claims
- 0672US12183696B2Semiconductor device including bonding pad metal layer structureINFINEON TECHNOLOGIES AG·Filed 2023·Granted Dec 31, 2024·0 cites·25 claims
- 0770US6274440B1Manufacturing of cavity fuses on gate conductor levelIBM·Filed 1999·Granted Aug 14, 2001·39 cites·16 claims
- 0869US11329126B2Method of manufacturing a superjunction semiconductor deviceINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2018·Granted May 10, 2022·1 cites·20 claims
- 0967US6486505B1Semiconductor contact and method of forming the sameINFINEON TECHNOLOGIES CORP·Filed 2000·Granted Nov 26, 2002·11 cites·8 claims
- 1065US6960523B2Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM deviceIBM·Filed 2003·Granted Nov 1, 2005·10 cites·15 claims
- 1164US6204187B1Contact and deep trench patterningINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Mar 20, 2001·31 cites·21 claims
- 1263US11764176B2Semiconductor device including bonding pad metal layer structureINFINEON TECHNOLOGIES AG·Filed 2021·Granted Sep 19, 2023·0 cites·18 claims
- 1358US6444531B1Disposable spacer technology for device tailoringINFINEON TECHNOLOGIES AG·Filed 2000·Granted Sep 3, 2002·8 cites·14 claims
- 1449US6255158B1Process of manufacturing a vertical dynamic random access memory deviceIBM·Filed 2000·Granted Jul 3, 2001·3 cites·5 claims
- 1542US6699750B1Vertical device formed adjacent to a wordline sidewall and method for semiconductor chipsINFINEON TECHNOLOGIES CORP·Filed 1998·Granted Mar 2, 2004·6 cites·15 claims
- 1636US6268293B1Method of forming wires on an integrated circuit chipIBM·Filed 1999·Granted Jul 31, 2001·8 cites·12 claims
- 1736US2005014332A1Method to improve bitline contact formation using a line maskINFINEON TECHNOLOGIES CORP·Filed 2003·Application pending·0 cites
- 1835US2005048715A1Trench capacitor with pillarFiled 2003·Application pending·0 cites
- 1934US6096664AMethod of manufacturing semiconductor structures including a pair of MOSFETsSIEMENS AG·Filed 1998·Granted Aug 1, 2000·4 cites·26 claims
- 2033US6210995B1Method for manufacturing fusible links in a semiconductor deviceIBM·Filed 1999·Granted Apr 3, 2001·4 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →