Inventor · disambiguated record
Keith R. Schakel
Also filed as: SCHAKEL KEITH · SCHAKEL KEITH R
53 granted patents·11 pending applications·3,456 citations·filing 1999–2016
99Inventor score
Files withRAJAN SURESH NATARAJAN23METARAM INC9GOOGLE INC8ADVANCED MICRO DEVICES INC7SCHAKEL KEITH R6
Top patents by PatentIndex Score
64 records- 0199US9171585B2Configurable memory circuit system and methodGOOGLE INC·Filed 2013·Granted Oct 27, 2015·65 cites·20 claims
- 0299US8667312B2Performing power management operationsRAJAN SURESH NATARAJAN·Filed 2012·Granted Mar 4, 2014·76 cites·20 claims
- 0399US8181048B2Performing power management operationsRAJAN SURESH NATARAJAN·Filed 2010·Granted May 15, 2012·67 cites·34 claims
- 0499US7761724B2Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuitGOOGLE INC·Filed 2008·Granted Jul 20, 2010·138 cites·28 claims
- 0599US7730338B2Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuitsGOOGLE INC·Filed 2008·Granted Jun 1, 2010·135 cites·29 claims
- 0699US7724589B2System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuitsGOOGLE INC·Filed 2006·Granted May 25, 2010·140 cites·23 claims
- 0799US7609567B2System and method for simulating an aspect of a memory circuitMETARAM INC·Filed 2006·Granted Oct 27, 2009·136 cites·28 claims
- 0899US7590796B2System and method for power management in memory systemsMETARAM INC·Filed 2006·Granted Sep 15, 2009·141 cites·20 claims
- 0999US7581127B2Interface circuit system and method for performing power saving operations during a command-related latencyMETARAM INC·Filed 2006·Granted Aug 25, 2009·137 cites·26 claims
- 1099US7472220B2Interface circuit system and method for performing power management operations utilizing power management signalsMETARAM INC·Filed 2006·Granted Dec 30, 2008·152 cites·18 claims
- 1199US7392338B2Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuitsMETARAM INC·Filed 2006·Granted Jun 24, 2008·137 cites·16 claims
- 1299US7386656B2Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuitMETARAM INC·Filed 2006·Granted Jun 10, 2008·147 cites·19 claims
- 1398US8773937B2Memory refresh apparatus and methodSCHAKEL KEITH R·Filed 2011·Granted Jul 8, 2014·64 cites·19 claims
- 1498US8745321B2Simulating a memory standardRAJAN SURESH NATARAJAN·Filed 2012·Granted Jun 3, 2014·68 cites·13 claims
- 1598US8671244B2Simulating a memory standardRAJAN SURESH NATARAJAN·Filed 2011·Granted Mar 11, 2014·66 cites·13 claims
- 1698US8601204B2Simulating a refresh operation latencyRAJAN SURESH NATARAJAN·Filed 2011·Granted Dec 3, 2013·70 cites·19 claims
- 1798US8595419B2Memory apparatus operable to perform a power-saving operationRAJAN SURESH NATARAJAN·Filed 2011·Granted Nov 26, 2013·68 cites·31 claims
- 1898US8566516B2Refresh management of memory modulesSCHAKEL KEITH R·Filed 2007·Granted Oct 22, 2013·76 cites·24 claims
- 1998US8566556B2Memory module with memory stack and interface with enhanced capabilitiesRAJAN SURESH NATARAJAN·Filed 2011·Granted Oct 22, 2013·68 cites·20 claims
- 2098US8359187B2Simulating a different number of memory circuit devicesGOOGLE INC·Filed 2006·Granted Jan 22, 2013·66 cites·39 claims
- 2198US8340953B2Memory circuit simulation with power saving capabilitiesRAJAN SURESH NATARAJAN·Filed 2006·Granted Dec 25, 2012·75 cites·32 claims
- 2298US8280714B2Memory circuit simulation system and method with refresh capabilitiesRAJAN SURESH NATARAJAN·Filed 2006·Granted Oct 2, 2012·66 cites·33 claims
- 2398US8244971B2Memory circuit system and methodRAJAN SURESH NATARAJAN·Filed 2007·Granted Aug 14, 2012·86 cites·33 claims
- 2498US8154935B2Delaying a signal communicated from a system to at least one of a plurality of memory circuitsRAJAN SURESH NATARAJAN·Filed 2010·Granted Apr 10, 2012·69 cites·37 claims
- 2598US8112266B2Apparatus for simulating an aspect of a memory circuitRAJAN SURESH NATARAJAN·Filed 2007·Granted Feb 7, 2012·70 cites·19 claims
- 2698US8090897B2System and method for simulating an aspect of a memory circuitRAJAN SURESH NATARAJAN·Filed 2007·Granted Jan 3, 2012·73 cites·20 claims
- 2798US8041881B2Memory device with emulated characteristicsGOOGLE INC·Filed 2007·Granted Oct 18, 2011·75 cites·25 claims
- 2898US8019589B2Memory apparatus operable to perform a power-saving operationGOOGLE INC·Filed 2007·Granted Sep 13, 2011·80 cites·17 claims
- 2998US7580312B2Power saving system and method for use with a plurality of memory circuitsMETARAM INC·Filed 2006·Granted Aug 25, 2009·134 cites·27 claims
- 3097US8209479B2Memory circuit system and methodRAJAN SURESH NATARAJAN·Filed 2007·Granted Jun 26, 2012·85 cites·32 claims
- 3197US8089795B2Memory module with memory stack and interface with enhanced capabilitiesRAJAN SURESH N·Filed 2007·Granted Jan 3, 2012·136 cites·20 claims
- 3297US8077535B2Memory refresh apparatus and methodSCHAKEL KEITH R·Filed 2006·Granted Dec 13, 2011·70 cites·34 claims
- 3394US8868829B2Memory circuit system and methodRAJAN SURESH NATARAJAN·Filed 2012·Granted Oct 21, 2014·17 cites·24 claims
- 3493US6502185B1Pipeline elements which verify predecode informationADVANCED MICRO DEVICES INC·Filed 2000·Granted Dec 31, 2002·92 cites·22 claims
- 3592US8797779B2Memory module with memory stack and interface with enhanced capabilitesRAJAN SURESH NATARAJAN·Filed 2012·Granted Aug 5, 2014·12 cites·20 claims
- 3690US7215680B2Method and apparatus for scheduling packet flow on a fibre channel arbitrated loopNISHAN SYSTEMS INC·Filed 2002·Granted May 8, 2007·77 cites·47 claims
- 3789US6622237B1Store to load forward predictor training using delta tagADVANCED MICRO DEVICES INC·Filed 2000·Granted Sep 16, 2003·59 cites·20 claims
- 3888US6687789B1Cache which provides partial tags from non-predicted ways to direct search if way prediction missesADVANCED MICRO DEVICES INC·Filed 2000·Granted Feb 3, 2004·53 cites·33 claims
- 3985US10013371B2Configurable memory circuit system and methodGOOGLE LLC·Filed 2016·Granted Jul 3, 2018·4 cites·20 claims
- 4082US8949519B2Simulating a memory circuitRAJAN SURESH NATARAJAN·Filed 2009·Granted Feb 3, 2015·11 cites·20 claims
- 4174US7283556B2Method and system for managing time division multiplexing (TDM) timeslots in a network switchNISHAN SYSTEMS INC·Filed 2002·Granted Oct 16, 2007·10 cites·41 claims
- 4272US7227841B2Packet input thresholding for resource distribution in a network switchNISHAN SYSTEMS INC·Filed 2002·Granted Jun 5, 2007·18 cites·43 claims
- 4371US9507739B2Configurable memory circuit system and methodGOOGLE INC·Filed 2015·Granted Nov 29, 2016·3 cites·20 claims
- 4467US9542353B2System and method for reducing command scheduling constraints of memory circuitsRAJAN SURESH NATARAJAN·Filed 2007·Granted Jan 10, 2017·5 cites·14 claims
- 4566US7809852B2High jitter scheduling of interleaved frames in an arbitrated loopBROCADE COMM SYSTEMS INC·Filed 2002·Granted Oct 5, 2010·10 cites·40 claims
- 4664US9542352B2System and method for reducing command scheduling constraints of memory circuitsRAJAN SURESH NATARAJAN·Filed 2007·Granted Jan 10, 2017·2 cites·18 claims
- 4762US7406041B2System and method for late-dropping packets in a network switchBROCADE COMM SYSTEMS INC·Filed 2002·Granted Jul 29, 2008·7 cites·36 claims
- 4853US9632929B2Translating an address associated with a command communicated between a system and memory circuitsRAJAN SURESH NATARAJAN·Filed 2007·Granted Apr 25, 2017·0 cites·19 claims
- 4951US2008028136A1Method and apparatus for refresh management of memory modulesSCHAKEL KEITH R·Filed 2007·Application pending·0 cites
- 5051US2013132661A1Method and apparatus for refresh management of memory modulesSCHAKEL KEITH R·Filed 2012·Application pending·0 cites
Showing the top 50 of 64 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Keith R. Schakel files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →