Inventor · disambiguated record
Tamer Mohammed Ali
Also filed as: ALI TAMER · ALI TAMER M · ALI TAMER MOHAMMED
32 granted patents·4 pending applications·75 citations·filing 2009–2023
95Inventor score
Top patents by PatentIndex Score
36 records- 0194US9685969B1Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibrationAVAGO TECHNOLOGIES GENERAL IP·Filed 2016·Granted Jun 20, 2017·19 cites·20 claims
- 0288US11552830B2Low power receiver with equalization circuit, communication unit and method thereforMEDIATEK SINGAPORE PTE LTD·Filed 2021·Granted Jan 10, 2023·4 cites·20 claims
- 0385US8994399B2Transmission line driver with output swing controlBROADCOM CORP·Filed 2013·Granted Mar 31, 2015·8 cites·20 claims
- 0481US10732215B2Systems and methods for on-chip time-domain reflectometryMEDIATEK SINGAPORE PTE LTD·Filed 2018·Granted Aug 4, 2020·2 cites·6 claims
- 0581US8664973B2Common mode termination with C-multiplier circuitALI TAMER·Filed 2012·Granted Mar 4, 2014·7 cites·20 claims
- 0679US10651825B2Resistor-based attenuator systemsMEDIATEK SINGAPORE PTE LTD·Filed 2019·Granted May 12, 2020·3 cites·19 claims
- 0777US9136904B2High bandwidth equalizer and limiting amplifierALI TAMER·Filed 2012·Granted Sep 15, 2015·5 cites·20 claims
- 0875US8958501B2Quasi-digital receiver for high speed SER-DESBROADCOM CORP·Filed 2012·Granted Feb 17, 2015·4 cites·20 claims
- 0973US9503114B1Time interleaving structure for a multi-lane analog-to-digital converter (ADC)BROADCOM CORP·Filed 2015·Granted Nov 22, 2016·3 cites·20 claims
- 1071US8116420B2Clock-forwarding technique for high-speed linksALI TAMER M·Filed 2009·Granted Feb 14, 2012·6 cites·20 claims
- 1169US7994832B2Aperture generating circuit for a multiplying delay-locked loopORACLE AMERICA INC·Filed 2009·Granted Aug 9, 2011·6 cites·20 claims
- 1268US9246670B2Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDesBROADCOM CORP·Filed 2015·Granted Jan 26, 2016·2 cites·20 claims
- 1368US9024659B2Method and apparatus for passive equalization and slew-rate controlBROADCOM CORP·Filed 2013·Granted May 5, 2015·2 cites·20 claims
- 1466US11923819B2Wideband signal attenuatorMEDIATEK SINGAPORE PTE LTD·Filed 2022·Granted Mar 5, 2024·0 cites·20 claims
- 1564US9184737B1Process mitigated clock skew adjustmentBROADCOM CORP·Filed 2014·Granted Nov 10, 2015·1 cites·20 claims
- 1661US12381563B2Digital phase-locked loop and related merged duty cycle calibration scheme for frequency synthesizersMEDIATEK INC·Filed 2023·Granted Aug 5, 2025·0 cites·20 claims
- 1761US12316333B2Apparatus and method for optimum loop gain calibration for clock data recovery and phase locked loopMEDIATEK INC·Filed 2023·Granted May 27, 2025·0 cites·20 claims
- 1860US8035436B2Passive capacitively injected phase interpolatorORACLE AMERICA INC·Filed 2009·Granted Oct 11, 2011·2 cites·20 claims
- 1958US11221379B2Systems and methods for on-chip time-domain reflectometryMEDIATEK SINGAPORE PTE LTD·Filed 2020·Granted Jan 11, 2022·0 cites·20 claims
- 2058US9001869B2Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDesBROADCOM CORP·Filed 2013·Granted Apr 7, 2015·1 cites·20 claims
- 2156US12413235B2Digitally controlled delay line gain calibration using error injectionMEDIATEK INC·Filed 2023·Granted Sep 9, 2025·0 cites·20 claims
- 2255US12407341B2Multi-stage digitally controlled delay line linearity enhancing by redundancy and randomizationMEDIATEK INC·Filed 2023·Granted Sep 2, 2025·0 cites·20 claims
- 2352US2024146269A1Differential all-pass coupling circuit with common mode feedbackMEDIATEK INC·Filed 2023·Application pending·0 cites
- 2450US11894956B2Continuous time linear equalizer with a plurality of signal pathsMEDIATEK SINGAPORE PTE LTD·Filed 2022·Granted Feb 6, 2024·0 cites·20 claims
- 2549US12388431B2Gain calibration of digitally controlled delay lineMEDIATEK INC·Filed 2023·Granted Aug 12, 2025·0 cites·20 claims
- 2649US11469729B2Hybrid receiver front-endMEDIATEK SINGAPORE PTE LTD·Filed 2020·Granted Oct 11, 2022·0 cites·16 claims
- 2748US10804924B2Systems for reducing pattern-dependent inter-symbol interference and related methodsMEDIATEK SINGAPORE PTE LTD·Filed 2019·Granted Oct 13, 2020·0 cites·20 claims
- 2847US2016036538A1Process Mitigated Clock Skew AdjustmentBROADCOM CORP·Filed 2015·Application pending·0 cites
- 2946US2024171167A1Enhancement of linearity for digitally controlled delay lineMEDIA TEK INC·Filed 2023·Application pending·0 cites
- 3045US12451900B2Analog assisted feed-forward equalizerMEDIATEK INC·Filed 2023·Granted Oct 21, 2025·0 cites·20 claims
- 3145US9780777B1Methods and apparatus for level-shifting high speed serial data with low power consumptionMEDIATEK INC·Filed 2016·Granted Oct 3, 2017·0 cites·20 claims
- 3242US10734958B2Low-voltage high-speed receiverMEDIATEK INC·Filed 2017·Granted Aug 4, 2020·0 cites·19 claims
- 3341US10027341B2Multiple sampling stage receiver and related methodsMEDIATEK INC·Filed 2017·Granted Jul 17, 2018·0 cites·22 claims
- 3440US10009023B2Method and apparatus for edge equalization for high speed driversMEDIATEK INC·Filed 2016·Granted Jun 26, 2018·0 cites·17 claims
- 3538US2019304899A1Methods and systems for supply noise suppression in systems-on-chipMEDIATEK SINGAPORE PTE LTD·Filed 2018·Application pending·0 cites
- 3636US11025240B2Circuits for delay mismatch compensation and related methodsMEDIATEK INC·Filed 2017·Granted Jun 1, 2021·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →