Inventor · disambiguated record
Mohammad H. Movahed-Ezazi
Also filed as: MOVAHED EZAZI MOHAMMAD · MOVAHED-EZAZI MOHAMMAD H · MOVAHED-EZAZI MOHAMMAD HOMAYOUN
15 granted patents·3 pending applications·68 citations·filing 2007–2018
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
18 records- 0190US8448111B2System and method for metastability verification of circuits of an integrated circuitMNEIMNEH MAHER·Filed 2011·Granted May 21, 2013·30 cites·10 claims
- 0285US8533647B1Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) designATRENTA INC·Filed 2012·Granted Sep 10, 2013·13 cites·12 claims
- 0384US8656326B1Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline designATRENTA INC·Filed 2013·Granted Feb 18, 2014·7 cites·6 claims
- 0482US8856706B2System and method for metastability verification of circuits of an integrated circuitATRENTA INC·Filed 2013·Granted Oct 7, 2014·7 cites·26 claims
- 0572US8607173B2Hierarchical bottom-up clock domain crossing verificationSARWARY MOHAMED SHAKER·Filed 2012·Granted Dec 10, 2013·4 cites·12 claims
- 0664US8677295B1Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline designATRENTA INC·Filed 2013·Granted Mar 18, 2014·1 cites·5 claims
- 0762US8984469B2System and method for strengthening of a circuit element to reduce an integrated circuit's power consumptionATRENTA INC·Filed 2013·Granted Mar 17, 2015·1 cites·14 claims
- 0861US9721057B2System and method for netlist clock domain crossing verificationSYNOPSYS INC·Filed 2015·Granted Aug 1, 2017·1 cites·18 claims
- 0961US8635578B1System and method for strengthening of a circuit element to reduce an integrated circuit's power consumptionATRENTA INC·Filed 2013·Granted Jan 21, 2014·1 cites·11 claims
- 1060US9201992B2Method and apparatus using formal methods for checking generated-clock timing definitionsSYNOPSYS INC·Filed 2014·Granted Dec 1, 2015·1 cites·16 claims
- 1158US9721058B2System and method for reactive initialization based formal verification of electronic logic designSYNOPSYS INC·Filed 2015·Granted Aug 1, 2017·1 cites·16 claims
- 1258US8788993B2Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) designATRENTA INC·Filed 2013·Granted Jul 22, 2014·1 cites·12 claims
- 1349US2015143307A1Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline designRAHIM SOLAIMAN·Filed 2014·Application pending·0 cites
- 1448US8984457B2System and method for a hybrid clock domain crossing verificationATRENTA INC·Filed 2013·Granted Mar 17, 2015·0 cites·17 claims
- 1544US10599800B2Formal clock network analysis, visualization, verification and generationSYNOPSYS INC·Filed 2018·Granted Mar 24, 2020·0 cites·20 claims
- 1643US2014282322A1System and method for filtration of error reports respective of static and quasi-static signals within an integrated circuit designATRENTA INC·Filed 2013·Application pending·0 cites
- 1742US8739087B1System and method for large multiplexer identification and creation in a design of an integrated circuitATRENTA INC·Filed 2013·Granted May 27, 2014·0 cites·19 claims
- 1839US2008201671A1Method for generating timing exceptionsATRENTA INC·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →