Inventor · disambiguated record
Solaiman Rahim
Also filed as: RAHIM SOLAIMAN
19 granted patents·2 pending applications·36 citations·filing 2007–2023
91Inventor score
Top patents by PatentIndex Score
21 records- 0184US11842132B1Multi-cycle power analysis of integrated circuit designsSYNOPSYS INC·Filed 2022·Granted Dec 12, 2023·1 cites·12 claims
- 0284US8656326B1Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline designATRENTA INC·Filed 2013·Granted Feb 18, 2014·7 cites·6 claims
- 0382US12124780B2Power estimation using input vectors and deep recurrent neural networksSYNOPSYS INC·Filed 2021·Granted Oct 22, 2024·1 cites·18 claims
- 0482US11651129B2Selecting a subset of training data from a data pool for a power prediction modelSYNOPSYS INC·Filed 2021·Granted May 16, 2023·1 cites·19 claims
- 0581US7650581B2Method for modeling and verifying timing exceptionsATRENTA INC·Filed 2007·Granted Jan 19, 2010·11 cites·19 claims
- 0673US12001317B2Waveform based reconstruction for emulationSYNOPSYS INC·Filed 2023·Granted Jun 4, 2024·0 cites·20 claims
- 0772US10621296B1Generating SAIF efficiently from hardware platformsSYNOPSYS INC·Filed 2018·Granted Apr 14, 2020·2 cites·16 claims
- 0872US8285527B2Method and system for equivalence checkingRAHIM SOLAIMAN·Filed 2010·Granted Oct 9, 2012·5 cites·15 claims
- 0970US12093620B1Multi-cycle power analysis of integrated circuit designsSYNOPSYS INC·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 1067US11726899B2Waveform based reconstruction for emulationSYNOPSYS INC·Filed 2021·Granted Aug 15, 2023·0 cites·20 claims
- 1164US8677295B1Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline designATRENTA INC·Filed 2013·Granted Mar 18, 2014·1 cites·5 claims
- 1264US8042085B2Method for compaction of timing exception pathsATRENTA INC·Filed 2008·Granted Oct 18, 2011·5 cites·16 claims
- 1362US8984469B2System and method for strengthening of a circuit element to reduce an integrated circuit's power consumptionATRENTA INC·Filed 2013·Granted Mar 17, 2015·1 cites·14 claims
- 1461US8635578B1System and method for strengthening of a circuit element to reduce an integrated circuit's power consumptionATRENTA INC·Filed 2013·Granted Jan 21, 2014·1 cites·11 claims
- 1555US11200149B2Waveform based reconstruction for emulationSYNOPSYS INC·Filed 2017·Granted Dec 14, 2021·0 cites·20 claims
- 1654US12254255B1Glitch identification and power analysis using simulation vectorsSYNOPSYS INC·Filed 2022·Granted Mar 18, 2025·0 cites·20 claims
- 1749US11651131B2Glitch source identification and rankingSYNOPSYS INC·Filed 2021·Granted May 16, 2023·0 cites·20 claims
- 1849US2015143307A1Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline designRAHIM SOLAIMAN·Filed 2014·Application pending·0 cites
- 1945US12001768B1Enhanced glitch estimation in vectorless power analysisSYNOPSYS INC·Filed 2021·Granted Jun 4, 2024·0 cites·18 claims
- 2039US2008201671A1Method for generating timing exceptionsATRENTA INC·Filed 2007·Application pending·0 cites
- 2137US9405872B2System and method for reducing power of a circuit using critical signal analysisSYNOPSYS INC·Filed 2015·Granted Aug 2, 2016·0 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →