Inventor · disambiguated record
Dusan Petranovic
Also filed as: PETRANOVIC DUSAN
15 granted patents·1 pending application·537 citations·filing 1998–2010
94Inventor score
Top patents by PatentIndex Score
16 records- 0192US6263299B1Geometric aerial image simulationLSI LOGIC CORP·Filed 1999·Granted Jul 17, 2001·170 cites·29 claims
- 0291US6499003B2Method and apparatus for application of proximity correction with unitary segmentationLSI LOGIC CORP·Filed 1998·Granted Dec 24, 2002·88 cites·13 claims
- 0389US6171731B1Hybrid aerial image simulationLSI LOGIC CORP·Filed 1999·Granted Jan 9, 2001·103 cites·19 claims
- 0487US6546541B1Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitancesLSI LOGIC CORP·Filed 2001·Granted Apr 8, 2003·52 cites·20 claims
- 0583US7689962B2Extracting high frequency impedance in a circuit design using an electronic design automation toolSUAYA ROBERTO·Filed 2007·Granted Mar 30, 2010·13 cites·54 claims
- 0679US7467359B2Decoder using a memory for storing state metrics implementing a decoder trellisLSI CORP·Filed 2005·Granted Dec 16, 2008·10 cites·5 claims
- 0779US6532585B1Method and apparatus for application of proximity correction with relative segmentationLSI LOGIC CORP·Filed 2000·Granted Mar 11, 2003·15 cites·35 claims
- 0876US7900184B2Decoder using a memory for storing state metrics implementing a decoder trellisLSI CORP·Filed 2008·Granted Mar 1, 2011·8 cites·20 claims
- 0972US8667446B2Extracting high frequency impedance in a circuit design using an electronic design automation toolSUAYA ROBERTO·Filed 2010·Granted Mar 4, 2014·3 cites·22 claims
- 1070US6175953B1Method and apparatus for general systematic application of proximity correctionLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·29 cites·30 claims
- 1159US6948114B2Multi-resolution Viterbi decoding techniqueLSI LOGIC CORP·Filed 2002·Granted Sep 20, 2005·10 cites·20 claims
- 1254US6174630B1Method of proximity correction with relative segmentationLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·12 cites·18 claims
- 1351US7017126B2Metacores: design and optimization techniquesLSI LOGIC CORP·Filed 2002·Granted Mar 21, 2006·8 cites·19 claims
- 1438US6901571B1Timing-driven placement method utilizing novel interconnect delay modelLSI LOGIC CORP·Filed 1998·Granted May 31, 2005·10 cites·12 claims
- 1531US6109201AResynthesis method for significant delay reductionLSI LOGIC CORP·Filed 1998·Granted Aug 29, 2000·6 cites·17 claims
- 1631US2011185323A1Stacked Integracted Circuit VerificationHOGAN WILLIAM MATTHEW·Filed 2010·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Dusan Petranovic files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →