Inventor · disambiguated record
Rebecca L. Stamm
Also filed as: STAMM REBECCA · STAMM REBECCA L
14 granted patents·1 pending application·1,968 citations·filing 1988–2003
96Inventor score
Files withDIGITAL EQUIPMENT CORP10COMPAQ COMPUTER CORP2COMPAQ INFORMATION TECHNOLOGIE1HEWLETT PACKARD DEVELOPMENT CO1
Top patents by PatentIndex Score
15 records- 0198US5404482AProcessor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fillsDIGITAL EQUIPMENT CORP·Filed 1992·Granted Apr 4, 1995·208 cites·15 claims
- 0297US5481689AConversion of internal processor register commands to I/O space addressesDIGITAL EQUIPMENT CORP·Filed 1993·Granted Jan 2, 1996·95 cites·11 claims
- 0395US6493741B1Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unitCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Dec 10, 2002·211 cites·60 claims
- 0494US6675192B2Temporary halting of thread execution until monitoring of armed events to memory location identified in working registersHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 6, 2004·92 cites·5 claims
- 0594US6470443B1Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count informationCOMPAQ COMPUTER CORP·Filed 2000·Granted Oct 22, 2002·104 cites·8 claims
- 0693US5432918AMethod and apparatus for ordering read and write operations using conflict bits in a write queueDIGITAL EQUIPMENT CORP·Filed 1992·Granted Jul 11, 1995·213 cites·18 claims
- 0791US5347648AEnsuring write ordering under writeback cache error conditionsDIGITAL EQUIPMENT CORP·Filed 1992·Granted Sep 13, 1994·188 cites·20 claims
- 0891US5148536APipeline having an integral cache which processes cache misses and loads data in parallelDIGITAL EQUIPMENT CORP·Filed 1988·Granted Sep 15, 1992·126 cites·27 claims
- 0989US6073159AThread properties attribute vector based thread selection in multithreading processorCOMPAQ COMPUTER CORP·Filed 1996·Granted Jun 6, 2000·150 cites·71 claims
- 1089US5317720AProcessor system with writeback cache using writeback and non writeback transactions stored in separate queuesDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 31, 1994·168 cites·30 claims
- 1186US5155843AError transition mode for multi-processor systemDIGITAL EQUIPMENT CORP·Filed 1990·Granted Oct 13, 1992·143 cites·15 claims
- 1284US5404483AProcessor and method for delaying the processing of cache coherency transactions during outstanding cache fillsDIGITAL EQUIPMENT CORP·Filed 1992·Granted Apr 4, 1995·119 cites·19 claims
- 1384US5058006AMethod and apparatus for filtering invalidate requestsDIGITAL EQUIPMENT CORP·Filed 1988·Granted Oct 15, 1991·86 cites·6 claims
- 1476US5430888APipeline utilizing an integral cache for transferring data to and from a registerDIGITAL EQUIPMENT CORP·Filed 1993·Granted Jul 4, 1995·65 cites·2 claims
- 1546US2004073905A1Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unitFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →