Inventor · disambiguated record
Roger D. Arnold
Also filed as: ARNOLD ROGER · ARNOLD ROGER D
16 granted patents·4 pending applications·437 citations·filing 1985–2006
95Inventor score
Files withINFINEON TECHNOLOGIES AG8INFINEON TECHNOLOGIES CORP4SIEMENS AG3UBICOM INC2ABB RESEARCH LTD1
Top patents by PatentIndex Score
20 records- 0185US7546442B1Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructionsUBICOM INC·Filed 2006·Granted Jun 9, 2009·14 cites·16 claims
- 0282US7047396B1Fixed length memory to memory arithmetic and architecture for a communications embedded processor systemUBICOM INC·Filed 2001·Granted May 16, 2006·34 cites·8 claims
- 0380US7263599B2Thread ID in a multithreaded processorINFINEON TECHNOLOGIES AG·Filed 2004·Granted Aug 28, 2007·31 cites·15 claims
- 0477US7260707B2Variable length instruction pipelineINFINEON TECHNOLOGIES AG·Filed 2005·Granted Aug 21, 2007·7 cites·19 claims
- 0577US7062606B2Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking eventsINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jun 13, 2006·23 cites·29 claims
- 0677US4583725APatient support frame for posterior lumbar laminectomyARNOLD ROGER D·Filed 1985·Granted Apr 22, 1986·66 cites·2 claims
- 0776US6128641AData processing unit with hardware assisted context switching capabilitySIEMENS AG·Filed 1997·Granted Oct 3, 2000·80 cites·24 claims
- 0874US6859873B2Variable length instruction pipelineINFINEON TECHNOLOGIES AG·Filed 2001·Granted Feb 22, 2005·17 cites·8 claims
- 0971US7159103B2Zero-overhead loop operation in microprocessor having instruction bufferINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jan 2, 2007·17 cites·28 claims
- 1062US7360203B2Program tracing in a multithreaded processorINFINEON TECHNOLOGIES AG·Filed 2004·Granted Apr 15, 2008·9 cites·30 claims
- 1160US6434689B2Data processing unit with interface for sharing registers by a processor and a coprocessorINFINEON TECHNOLOGIES CORP·Filed 1998·Granted Aug 13, 2002·40 cites·13 claims
- 1257US6175913B1Data processing unit with debug capabilities using a memory protection unitSIEMENS AG·Filed 1997·Granted Jan 16, 2001·32 cites·16 claims
- 1355US7774585B2Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operationINFINEON TECHNOLOGIES AG·Filed 2003·Granted Aug 10, 2010·4 cites·40 claims
- 1453US6292845B1Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectivelyINFINEON TECHNOLOGIES CORP·Filed 1998·Granted Sep 18, 2001·30 cites·14 claims
- 1545US6378065B1Apparatus with context switching capabilityINFINEON TECHNOLOGIES CORP·Filed 1998·Granted Apr 23, 2002·18 cites·38 claims
- 1644US2005108711A1Machine instruction for enhanced control of multiple virtual processor systemsINFINEON TECHNOLOGIES CORP·Filed 2003·Application pending·0 cites
- 1743US6041387AApparatus for read/write-access to registers having register file architecture in a central processing unitSIEMENS AG·Filed 1997·Granted Mar 21, 2000·15 cites·11 claims
- 1842US2006259742A1Controlling out of order execution pipelines using pipeline skew parametersINFINEON TECHNOLOGIES AG·Filed 2005·Application pending·0 cites
- 1942US2005198475A1Thread selection unit and method to fairly allocate processor cycles in a block multithreaded processorINFINEON TECHNOLOGIES INC·Filed 2004·Application pending·0 cites
- 2040US2006129336A1Human machine interface for instruments and method to configure sameABB RESEARCH LTD·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →