Inventor · disambiguated record
Muthurajan Jayakumar
Also filed as: JAYAKUMAR MUTHURAJAN
15 granted patents·542 citations·filing 1993–2001
95Inventor score
Technology areasG06F
Files withINTEL CORP15
Top patents by PatentIndex Score
15 records- 0178US6108781ABootstrap processor selection architecture in SMP systemINTEL CORP·Filed 1999·Granted Aug 22, 2000·71 cites·9 claims
- 0271US6292906B1Method and apparatus for detecting and compensating for certain snoop errors in a system with multiple agents having cache memoriesINTEL CORP·Filed 1997·Granted Sep 18, 2001·62 cites·20 claims
- 0371US5904733ABootstrap processor selection architecture in SMP systemsINTEL CORP·Filed 1997·Granted May 18, 1999·53 cites·10 claims
- 0466US6021458AMethod and apparatus for handling multiple level-triggered and edge-triggered interruptsINTEL CORP·Filed 1998·Granted Feb 1, 2000·54 cites·21 claims
- 0563US5511200AMethod and apparatus for providing an enhanced programmable priority interrupt controllerINTEL CORP·Filed 1993·Granted Apr 23, 1996·38 cites·21 claims
- 0661US5961621AMechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined systemINTEL CORP·Filed 1997·Granted Oct 5, 1999·32 cites·9 claims
- 0759US5481725AMethod for providing programmable interrupts for embedded hardware used with programmable interrupt controllersINTEL CORP·Filed 1993·Granted Jan 2, 1996·42 cites·25 claims
- 0858US6012118AMethod and apparatus for performing bus operations in a computer system using deferred replies returned without using the address busINTEL CORP·Filed 1997·Granted Jan 4, 2000·34 cites·39 claims
- 0958US5889978AEmulation of interrupt control mechanism in a multiprocessor systemINTEL CORP·Filed 1997·Granted Mar 30, 1999·34 cites·11 claims
- 1058US5848279AMechanism for delivering interrupt messagesINTEL CORP·Filed 1996·Granted Dec 8, 1998·30 cites·6 claims
- 1157US5964856AMechanism for data strobe pre-driving during master changeover on a parallel busINTEL CORP·Filed 1997·Granted Oct 12, 1999·34 cites·8 claims
- 1254US6298410B1Apparatus and method for initiating hardware priority management by software controlled register accessINTEL CORP·Filed 1997·Granted Oct 2, 2001·33 cites·22 claims
- 1347US6260091B1Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred replyINTEL CORP·Filed 1999·Granted Jul 10, 2001·19 cites·47 claims
- 1444USRE40921EMechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined systemINTEL CORP·Filed 2001·Granted Sep 22, 2009·0 cites·28 claims
- 1533US5951663AMethod and apparatus for tracking bus transactionsINTEL CORP·Filed 1997·Granted Sep 14, 1999·6 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →