Inventor · disambiguated record
Subhasish Mitra
Also filed as: MITRA SUBHASISH
20 granted patents·3 pending applications·273 citations·filing 2001–2023
94Inventor score
Files withINTEL CORP10UNIV LELAND STANFORD JUNIOR7COMMISSARIAT ENERGIE ATOMIQUE2MITRA SUBHASISH2PATIL NISHANT1
Top patents by PatentIndex Score
23 records- 0195US7278076B2System and scanout circuits with error resilience circuitINTEL CORP·Filed 2005·Granted Oct 2, 2007·37 cites·30 claims
- 0295US7278074B2System and shadow circuits with output joining circuitINTEL CORP·Filed 2005·Granted Oct 2, 2007·45 cites·26 claims
- 0391US7373572B2System pulse latch and shadow pulse latch coupled to output joining circuitINTEL CORP·Filed 2005·Granted May 13, 2008·32 cites·24 claims
- 0490US7185253B2Compacting circuit responsesINTEL CORP·Filed 2002·Granted Feb 27, 2007·40 cites·25 claims
- 0589US7409631B2Error-detection flip-flopINTEL CORP·Filed 2005·Granted Aug 5, 2008·17 cites·9 claims
- 0688US7188284B2Error detecting circuitINTEL CORP·Filed 2004·Granted Mar 6, 2007·42 cites·28 claims
- 0786US7523371B2System and shadow bistable circuits coupled to output joining circuitINTEL CORP·Filed 2005·Granted Apr 21, 2009·15 cites·34 claims
- 0884US9928150B2System and method for testing a logic-based processing deviceUNIV LELAND STANFORD JUNIOR·Filed 2014·Granted Mar 27, 2018·8 cites·28 claims
- 0979US6910173B2Word voter for redundant systemsUNIV LELAND STANFORD JUNIOR·Filed 2001·Granted Jun 21, 2005·30 cites·56 claims
- 1074US10528448B2Post-silicon validation and debug using symbolic quick error detectionUNIV LELAND STANFORD JUNIOR·Filed 2016·Granted Jan 7, 2020·3 cites·10 claims
- 1164US7911234B1Nanotube logic circuitsUNIV LELAND STANFORD JUNIOR·Filed 2008·Granted Mar 22, 2011·1 cites·24 claims
- 1262US8065634B1System and method for analyzing a nanotube logic circuitPATIL NISHANT·Filed 2008·Granted Nov 22, 2011·2 cites·18 claims
- 1359US9748421B2Multiple carbon nanotube transfer and its applications for making high-performance carbon nanotube field-effect transistor (CNFET), transparent electrodes, and three-dimensional integration of CNFETsMITRA SUBHASISH·Filed 2010·Granted Aug 29, 2017·1 cites·2 claims
- 1444US2025200258A1Generalized qed pre-silicon verification frameworkUNIV LELAND STANFORD JUNIOR·Filed 2023·Application pending·0 cites
- 1541US10120737B2Apparatus for detecting bugs in logic-based processing devicesUNIV LELAND STANFORD JUNIOR·Filed 2016·Granted Nov 6, 2018·0 cites·6 claims
- 1638US7814383B2Compacting circuit responsesMITRA SUBHASISH·Filed 2005·Granted Oct 12, 2010·0 cites·16 claims
- 1738US7574640B2Compacting circuit responsesINTEL CORP·Filed 2003·Granted Aug 11, 2009·0 cites·15 claims
- 1837US11217307B2Circuit and method for programming resistive memory cellsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted Jan 4, 2022·0 cites·15 claims
- 1937US2006143551A1Localizing error detection and recoveryINTEL CORP·Filed 2004·Application pending·0 cites
- 2036US12300347B2Reconfigurable memory module designed to implement computing operationsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2021·Granted May 13, 2025·0 cites·18 claims
- 2136US7240260B2Stimulus generationINTEL CORP·Filed 2002·Granted Jul 3, 2007·0 cites·32 claims
- 2231US10546079B2System-level validation of systems-on-a-chip (SoC)UNIV LELAND STANFORD JUNIOR·Filed 2016·Granted Jan 28, 2020·0 cites·10 claims
- 2331US2007164371A1Reliability degradation compensation using body biasTSCHANZ JAMES W·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →