Inventor · disambiguated record
Shantanu R. Rajwade
Also filed as: RAJWADE SHANTANU · RAJWADE SHANTANU R
35 granted patents·7 pending applications·133 citations·filing 2014–2025
96Inventor score
Files withINTEL CORP20Intel NDTM US LLC9MICRON TECHNOLOGY INC9SK HYNIX NAND PRODUCT SOLUTIONS CORP2LODESTAR LICENSING GROUP LLC1
Top patents by PatentIndex Score
42 records- 0197US9910594B2Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operationMICRON TECHNOLOGY INC·Filed 2015·Granted Mar 6, 2018·24 cites·34 claims
- 0297US9703494B1Method and apparatus for protecting lower page data during programming in NAND flashINTEL CORP·Filed 2016·Granted Jul 11, 2017·32 cites·20 claims
- 0394US10379738B2Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operationMICRON TECHNOLOGY INC·Filed 2017·Granted Aug 13, 2019·11 cites·14 claims
- 0494US10224107B1Method and apparatus for dynamically determining start program voltages for a memory deviceINTEL CORP·Filed 2017·Granted Mar 5, 2019·22 cites·20 claims
- 0592US9852065B1Method and apparatus for reducing data program completion overhead in NAND flashINTEL CORP·Filed 2016·Granted Dec 26, 2017·13 cites·20 claims
- 0691US11094386B1Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cellINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·20 claims
- 0786US10482974B1Operation of a memory device during programmingMICRON TECHNOLOGY INC·Filed 2018·Granted Nov 19, 2019·5 cites·20 claims
- 0883US11056203B1Boosted bitlines for storage cell programmed state verification in a memory arrayINTEL CORP·Filed 2020·Granted Jul 6, 2021·2 cites·24 claims
- 0981US11721396B2Configuration of a memory device for programming memory cellsMICRON TECHNOLOGY INC·Filed 2020·Granted Aug 8, 2023·1 cites·20 claims
- 1081US10777277B2Configuration of a memory device for programming memory cellsMICRON TECHNOLOGY INC·Filed 2019·Granted Sep 15, 2020·3 cites·20 claims
- 1179US2025308591A1Simultaneous Programming Of Multiple Sub-Blocks In Nand Memory StructuresIntel NDTM US LLC·Filed 2025·Application pending·0 cites
- 1278US12482523B2Configuration of a memory device for programming memory cellsLODESTAR LICENSING GROUP LLC·Filed 2023·Granted Nov 25, 2025·0 cites·20 claims
- 1377US9865357B1Performing read operations on a memory deviceINTEL CORP·Filed 2016·Granted Jan 9, 2018·4 cites·23 claims
- 1476US11182074B2Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operationMICRON TECHNOLOGY INC·Filed 2019·Granted Nov 23, 2021·2 cites·17 claims
- 1573US11698725B2Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operationMICRON TECHNOLOGY INC·Filed 2021·Granted Jul 11, 2023·0 cites·20 claims
- 1670US10453535B2Segmented erase in memoryINTEL CORP·Filed 2015·Granted Oct 22, 2019·3 cites·25 claims
- 1770US9977622B1Buffer operations in memoryMICRON TECHNOLOGY INC·Filed 2016·Granted May 22, 2018·2 cites·31 claims
- 1867US10289313B2Method and apparatus for improving sequential reading in NAND flashINTEL CORP·Filed 2016·Granted May 14, 2019·1 cites·21 claims
- 1967US2024347117A1Solid state drive (ssd) with in-flight erasure iteration suspensionSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2024·Application pending·0 cites
- 2062US12394497B2Efficient bitline stabilization for program inhibit in NAND arraysIntel NDTM US LLC·Filed 2023·Granted Aug 19, 2025·0 cites·18 claims
- 2161US12334152B2Simultaneous programming of multiple sub-blocks in NAND memory structuresIntel NDTM US LLC·Filed 2021·Granted Jun 17, 2025·0 cites·18 claims
- 2261US9418752B2Ramping inhibit voltage during memory programmingRAJWADE SHANTANU R·Filed 2014·Granted Aug 16, 2016·2 cites·20 claims
- 2360US12189955B2Skip program verify for dynamic start voltage samplingIntel NDTM US LLC·Filed 2022·Granted Jan 7, 2025·0 cites·20 claims
- 2456US12243590B2Method and apparatus for improving write uniformity in a memory deviceINTEL CORP·Filed 2021·Granted Mar 4, 2025·0 cites·20 claims
- 2550US10658053B2Ramping inhibit voltage during memory programmingINTEL CORP·Filed 2017·Granted May 19, 2020·0 cites·17 claims
- 2650US10430114B2Buffer operations in memoryMICRON TECHNOLOGY INC·Filed 2018·Granted Oct 1, 2019·0 cites·20 claims
- 2749US2024136002A1Simultaneous statistical multi-subblock verify for nand memoriesIntel NDTM US LLC·Filed 2023·Application pending·0 cites
- 2848US12322455B2Program verify process having placement aware pre-program verify (PPV) bucket size modulationIntel NDTM US LLC·Filed 2021·Granted Jun 3, 2025·0 cites·20 claims
- 2948US9792997B2Ramping inhibit voltage during memory programmingINTEL CORP·Filed 2016·Granted Oct 17, 2017·0 cites·17 claims
- 3047US12051472B2Solid state drive (SSD) with in-flight erasure iteration suspensionSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2019·Granted Jul 30, 2024·0 cites·18 claims
- 3147US10714186B2Method and apparatus for dynamically determining start program voltages for a memory deviceINTEL CORP·Filed 2019·Granted Jul 14, 2020·0 cites·20 claims
- 3246US12224019B2Cache processes with adaptive dynamic start voltage calculation for memory devicesINTEL CORP·Filed 2021·Granted Feb 11, 2025·0 cites·20 claims
- 3346US11004524B2SSD having a parallelized, multi-level program voltage verificationINTEL CORP·Filed 2019·Granted May 11, 2021·0 cites·20 claims
- 3445US12394492B2Memory cell sensing circuit with adjusted bias from pre-boost operationIntel NDTM US LLC·Filed 2020·Granted Aug 19, 2025·0 cites·22 claims
- 3545US12237023B2Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuitIntel NDTM US LLC·Filed 2020·Granted Feb 25, 2025·0 cites·21 claims
- 3644US2024071532A1Fast and efficient verify recovery and array discharge for 3d nand memory arraysIntel NDTM US LLC·Filed 2023·Application pending·0 cites
- 3743US12211563B2Dynamic gate steps for last-level programming to improve write performanceINTEL CORP·Filed 2021·Granted Jan 28, 2025·0 cites·20 claims
- 3842US11139036B2Using variable voltages to discharge electrons from a memory array during verify recovery operationsINTEL CORP·Filed 2020·Granted Oct 5, 2021·0 cites·22 claims
- 3941US2023044991A1Page map renumbering to reduce error correction failures and improve program time uniformityINTEL CORP·Filed 2021·Application pending·0 cites
- 4040US2019043567A1Temperature-dependent read operation time adjustment in non-volatile memory devicesINTEL CORP·Filed 2018·Application pending·0 cites
- 4136US10141071B2Predictive count fail byte (CFBYTE) for non-volatile memoryINTEL CORP·Filed 2015·Granted Nov 27, 2018·0 cites·20 claims
- 4234US2019006016A1Method, system, and apparatus for detecting failure of programming of a memory deviceINTEL CORP·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →