Inventor · disambiguated record
Olivier Weber
Also filed as: WEBER OLIVIER
18 granted patents·12 pending applications·76 citations·filing 2008–2025
90Inventor score
Files withST MICROELECTRONICS CROLLES 2 SAS15ST MICROELECTRONICS INT NV5ST MICROELECTRONICS ROUSSET3STMICROELECTRONICS FRANCE3COMMISSARIAT ENERGIE ATOMIQUE2
Top patents by PatentIndex Score
30 records- 0188US11653582B2Chip containing an onboard non-volatile memory comprising a phase-change materialST MICROELECTRONICS CROLLES 2 SAS·Filed 2018·Granted May 16, 2023·4 cites·19 claims
- 0287US8006410B2Shoe, particularly sport or leisure shoeDECATHLON SA·Filed 2008·Granted Aug 30, 2011·57 cites·12 claims
- 0384US9929146B2Method of forming MOS and bipolar transistorsST MICROELECTRONICS CROLLES 2 SAS·Filed 2017·Granted Mar 27, 2018·4 cites·18 claims
- 0481US9653538B2Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding deviceST MICROELECTRONICS CROLLES 2 SAS·Filed 2014·Granted May 16, 2017·4 cites·11 claims
- 0574US12144187B2Strained transistors and phase change memoryST MICROELECTRONICS CROLLES 2 SAS·Filed 2023·Granted Nov 12, 2024·0 cites·19 claims
- 0669US12232435B2Chip containing an onboard non-volatile memory comprising a phase-change materialST MICROELECTRONICS CROLLES 2 SAS·Filed 2023·Granted Feb 18, 2025·0 cites·17 claims
- 0769US10482957B2Resistive RAM memory cellST MICROELECTRONICS ROUSSET·Filed 2018·Granted Nov 19, 2019·2 cites·18 claims
- 0867US9190334B2SOI integrated circuit comprising adjacent cells of different typesTHOMAS OLIVIER·Filed 2012·Granted Nov 17, 2015·3 cites·13 claims
- 0966US11818901B2Integrated circuit including bipolar transistorsST MICROELECTRONICS ROUSSET·Filed 2021·Granted Nov 14, 2023·0 cites·19 claims
- 1065US11723220B2Strained transistors and phase change memoryST MICROELECTRONICS CROLLES 2 SAS·Filed 2021·Granted Aug 8, 2023·0 cites·20 claims
- 1163US2025226010A1Electronic deviceST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1262US9099354B2Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOSCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2014·Granted Aug 4, 2015·2 cites·6 claims
- 1361US12328858B2Silicon-on-insulator semiconductor device with a static random access memory circuitSTMICROELECTRONICS FRANCE·Filed 2023·Granted Jun 10, 2025·0 cites·22 claims
- 1459US2024332406A1Transistor manufacturing methodST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1558US2024306401A1Method of manufacturing an electronic chip comprising a memory circuitST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1656US2024014215A1Method for manufacturing high-voltage transistors on a silicon-on-insulator type bulkST MICROELECTRONICS CROLLES 2 SAS·Filed 2023·Application pending·0 cites
- 1756US2023411450A1Electronic device manufacturing methodST MICROELECTRONICS CROLLES 2 SAS·Filed 2023·Application pending·0 cites
- 1855US11894382B2Set of integrated standard cellsSTMICROELECTRONICS FRANCE·Filed 2021·Granted Feb 6, 2024·0 cites·12 claims
- 1955US2024213153A1Electronic device with a cell of transistorsST MICROELECTRONICS CROLLES 2 SAS·Filed 2023·Application pending·0 cites
- 2055US2024147737A1Method of fabricating an electronic chip including a memory circuitST MICROELECTRONICS CROLLES 2 SAS·Filed 2023·Application pending·0 cites
- 2154US11152430B2Integrated circuit including bipolar transistorsST MICROELECTRONICS ROUSSET·Filed 2019·Granted Oct 19, 2021·0 cites·20 claims
- 2254US2024105730A1Set of integrated standard cellsSTMICROELECTRONICS FRANCE·Filed 2023·Application pending·0 cites
- 2354US2025357339A1Process of manufacturing an electronic device including a memory circuitST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 2454US2023387119A1Semiconductor device of the silicon on insulator type and corresponding manufacturing methodST MICROELECTRONICS CROLLES 2 SAS·Filed 2023·Application pending·0 cites
- 2553US10381478B2Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding deviceST MICROELECTRONICS CROLLES 2 SAS·Filed 2017·Granted Aug 13, 2019·0 cites·7 claims
- 2652US10381344B2Method of forming MOS and bipolar transistorsST MICROELECTRONICS CROLLES 2 SAS·Filed 2018·Granted Aug 13, 2019·0 cites·13 claims
- 2748US2025254992A1Electronic chip comprising stressed transistorsST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 2844US10332808B2Device comprising multiple gate structures and method of simultaneously manufacturing different transistorsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Granted Jun 25, 2019·0 cites·20 claims
- 2934US9876032B2Method of manufacturing a device with MOS transistorsST MICROELECTRONICS CROLLES 2 SAS·Filed 2016·Granted Jan 23, 2018·0 cites·18 claims
- 3034US2018097014A1Fdsoi-type field-effect transistorsST MICROELECTRONICS CROLLES 2 SAS·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →