Inventor · disambiguated record
Paul Allen Ganfield
Also filed as: GANFIELD PAUL A · GANFIELD PAUL ALLEN
44 granted patents·6 pending applications·379 citations·filing 1995–2021
97Inventor score
Top patents by PatentIndex Score
50 records- 0194US6158032AData processing system, circuit arrangement and program product including multi-path scan interface and methods thereofIBM·Filed 1998·Granted Dec 5, 2000·146 cites·37 claims
- 0287US11646861B2Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modesIBM·Filed 2021·Granted May 9, 2023·2 cites·25 claims
- 0384US7287103B2Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codesIBM·Filed 2005·Granted Oct 23, 2007·15 cites·20 claims
- 0480US9497020B1Initializing a descramblerIBM·Filed 2015·Granted Nov 15, 2016·3 cites·13 claims
- 0578US7467277B2Memory controller operating in a system with a variable system clockIBM·Filed 2006·Granted Dec 16, 2008·8 cites·9 claims
- 0676US7716430B2Separate handling of read and write of read-modify-writeIBM·Filed 2008·Granted May 11, 2010·6 cites·15 claims
- 0776US6178534B1System and method for using LBIST to find critical paths in functional logicIBM·Filed 1998·Granted Jan 23, 2001·38 cites·29 claims
- 0875US9515813B1Initializing a descramblerIBM·Filed 2015·Granted Dec 6, 2016·2 cites·13 claims
- 0974US9495314B2Determining command rate based on dropped commandsIBM·Filed 2014·Granted Nov 15, 2016·2 cites·7 claims
- 1074US9495312B2Determining command rate based on dropped commandsIBM·Filed 2013·Granted Nov 15, 2016·2 cites·15 claims
- 1173US10606777B2Dropped command truncation for efficient queue utilization in multiprocessor data processing systemIBM·Filed 2018·Granted Mar 31, 2020·1 cites·20 claims
- 1272US5663966ASystem and method for minimizing simultaneous switching during scan-based testingIBM·Filed 1996·Granted Sep 2, 1997·34 cites·41 claims
- 1371US7761682B2Memory controller operating in a system with a variable system clockIBM·Filed 2008·Granted Jul 20, 2010·4 cites·10 claims
- 1467US6195775B1Boundary scan latch configuration for generalized scan designsIBM·Filed 1998·Granted Feb 27, 2001·27 cites·28 claims
- 1565US9548857B2Initializing a descramblerIBM·Filed 2015·Granted Jan 17, 2017·1 cites·7 claims
- 1660US8510512B2Memory coherence directory supporting remotely sourced requests of nodal scopeGANFIELD PAUL A·Filed 2009·Granted Aug 13, 2013·2 cites·11 claims
- 1760US7752379B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2009·Granted Jul 6, 2010·1 cites·8 claims
- 1860US6909315B2Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)IBM·Filed 2002·Granted Jun 21, 2005·11 cites·28 claims
- 1959US8219745B2Memory controller to utilize DRAM write buffersBELLOWS MARK DAVID·Filed 2004·Granted Jul 10, 2012·11 cites·20 claims
- 2059US7240166B2Method and apparatus for implementing packet work area accesses and buffer sharingIBM·Filed 2003·Granted Jul 3, 2007·5 cites·20 claims
- 2158US7676639B2Separate handling of read and write of read-modify-writeIBM·Filed 2008·Granted Mar 9, 2010·1 cites·7 claims
- 2257US11907074B2Low-latency deserializer having fine granularity and defective-lane compensationIBM·Filed 2021·Granted Feb 20, 2024·0 cites·20 claims
- 2356US7363442B2Separate handling of read and write of read-modify-writeIBM·Filed 2004·Granted Apr 22, 2008·4 cites·2 claims
- 2455US10693595B2ACK clock compensation for high-speed serial communication interfacesIBM·Filed 2018·Granted Jun 23, 2020·0 cites·9 claims
- 2553US10664398B2Link-level cyclic redundancy check replay for non-blocking coherence flowIBM·Filed 2018·Granted May 26, 2020·0 cites·20 claims
- 2652US7487318B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2007·Granted Feb 3, 2009·0 cites·4 claims
- 2752US7266650B2Method, apparatus, and computer program product for implementing enhanced circular queue using loop countsIBM·Filed 2004·Granted Sep 4, 2007·2 cites·9 claims
- 2851US9565014B2Initializing a descramblerIBM·Filed 2015·Granted Feb 7, 2017·0 cites·7 claims
- 2951US5835502AMethod and apparatus for handling variable data word widths and array depths in a serial shared abist schemeIBM·Filed 1996·Granted Nov 10, 1998·14 cites·30 claims
- 3050US10128985B2ACK clock compensation for high-speed serial communication interfacesIBM·Filed 2016·Granted Nov 13, 2018·0 cites·14 claims
- 3150US7089387B2Methods and apparatus for maintaining coherency in a multi-processor systemIBM·Filed 2003·Granted Aug 8, 2006·1 cites·29 claims
- 3249US10969822B2Reducing time of day latency variation in a multi processor systemIBM·Filed 2019·Granted Apr 6, 2021·0 cites·18 claims
- 3349US7272699B2Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMsIBM·Filed 2004·Granted Sep 18, 2007·1 cites·14 claims
- 3448US8504779B2Memory coherence directory supporting remotely sourced requests of nodal scopeGANFIELD PAUL A·Filed 2012·Granted Aug 6, 2013·0 cites·6 claims
- 3548US7380052B2Reuse of functional data buffers for pattern buffers in XDR DRAMIBM·Filed 2004·Granted May 27, 2008·4 cites·8 claims
- 3648US7321950B2Method and apparatus for managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2005·Granted Jan 22, 2008·0 cites·14 claims
- 3748US7225097B2Methods and apparatus for memory calibrationIBM·Filed 2005·Granted May 29, 2007·2 cites·20 claims
- 3846US7248595B2Method, apparatus, and computer program product for implementing packet orderingIBM·Filed 2003·Granted Jul 24, 2007·0 cites·12 claims
- 3946US6260164B1SRAM that can be clocked on either clock phaseIBM·Filed 1998·Granted Jul 10, 2001·10 cites·13 claims
- 4046US5815694AApparatus and method to change a processor clock frequencyIBM·Filed 1995·Granted Sep 29, 1998·19 cites·17 claims
- 4146US2006129764A1Methods and apparatus for storing a commandIBM·Filed 2004·Application pending·0 cites
- 4245US7617332B2Method and apparatus for implementing packet command instructions for network processingIBM·Filed 2003·Granted Nov 10, 2009·0 cites·18 claims
- 4344US10324491B2Reducing time of day latency variation in a multi-processor systemIBM·Filed 2017·Granted Jun 18, 2019·0 cites·18 claims
- 4441US7925823B2Reuse of functional data buffers for pattern buffers in XDR DRAMIBM·Filed 2007·Granted Apr 12, 2011·0 cites·6 claims
- 4540US2008183916A1Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 4640US2008168206A1Methods and Apparatus for Interfacing a Processor and a MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 4739US2008229007A1Enhancements to an XDR Memory Controller to Allow for Conversion to DDR2BELLOWS MARK D·Filed 2007·Application pending·0 cites
- 4833US9838229B2Method for verifying the functionality of a digital circuitIBM·Filed 2015·Granted Dec 5, 2017·0 cites·17 claims
- 4930US2008168298A1Methods and Apparatus for Calibrating Heterogeneous Memory InterfacesBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 5028US2007121398A1Memory controller capable of handling precharge-to-precharge restrictionsBELLOWS MARK D·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →