Inventor · disambiguated record
Gregory Pribush
Also filed as: PRIBUSH GREGORY
8 granted patents·3 pending applications·76 citations·filing 1999–2014
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0185US8082430B2Representing a plurality of instructions with a fewer number of micro-operationsVALENTINE ROBERT·Filed 2005·Granted Dec 20, 2011·19 cites·28 claims
- 0280US8103858B2Efficient parallel floating point exception handling in a processorSPERBER ZEEV·Filed 2008·Granted Jan 24, 2012·14 cites·15 claims
- 0371US8782374B2Method and apparatus for inclusion of TLB entries in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Jul 15, 2014·6 cites·20 claims
- 0467US8127085B2Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Feb 28, 2012·4 cites·16 claims
- 0558US6950928B2Apparatus, method and system for fast register renaming using virtual renaming, including by using rename information or a renamed registerINTEL CORP·Filed 2001·Granted Sep 27, 2005·6 cites·34 claims
- 0652US6697933B1Method and apparatus for fast, speculative floating point register renamingINTEL CORP·Filed 2000·Granted Feb 24, 2004·4 cites·24 claims
- 0747US6757816B1Fast branch misprediction recovery method and systemINTEL CORP·Filed 1999·Granted Jun 29, 2004·23 cites·28 claims
- 0846US9092226B2Efficient parallel floating point exception handling in a processorSPERBER ZEEV·Filed 2011·Granted Jul 28, 2015·0 cites·11 claims
- 0945US2016026467A1Instruction and logic for executing instructions of multiple-widthsINTEL CORP·Filed 2014·Application pending·0 cites
- 1043US2005033942A1Distribution of architectural state information in a processor across multiple pipeline stagesFiled 2003·Application pending·0 cites
- 1143US2005060524A1Processor and methods for micro-operations generationFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →