Inventor · disambiguated record
Matthew B. Smittle
Also filed as: SMITTLE MATTHEW · SMITTLE MATTHEW B
16 granted patents·56 citations·filing 2009–2022
89Inventor score
Files withCADENCE DESIGN SYSTEMS INC5GOLLA ROBERT T3WESTERN DIGITAL TECH INC3ORACLE INT CORP2OLSON CHRISTOPHER H1
Top patents by PatentIndex Score
16 records- 0186US9058180B2Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructionsGOLLA ROBERT T·Filed 2009·Granted Jun 16, 2015·18 cites·20 claims
- 0286US8347309B2Dynamic mitigation of thread hogs on a threaded processorORACLE AMERICA INC·Filed 2009·Granted Jan 1, 2013·16 cites·18 claims
- 0382US9262171B2Dependency matrix for the determination of load dependenciesGOLLA ROBERT T·Filed 2009·Granted Feb 16, 2016·13 cites·18 claims
- 0481US9086890B2Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicatedOLSON CHRISTOPHER H·Filed 2012·Granted Jul 21, 2015·6 cites·12 claims
- 0561US8504805B2Processor operating mode for mitigating dependency conditions between instructions having different operand sizesGOLLA ROBERT T·Filed 2009·Granted Aug 6, 2013·2 cites·16 claims
- 0657US11537505B2Forced debug mode entryCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Dec 27, 2022·0 cites·17 claims
- 0755US12182016B1Memory circuit with power registersCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 31, 2024·0 cites·15 claims
- 0855US12141474B2Queue circuit for controlling access to a memory circuitCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Nov 12, 2024·0 cites·20 claims
- 0955US11740973B2Instruction error handlingCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 29, 2023·0 cites·19 claims
- 1055US11023342B2Cache diagnostic techniquesWESTERN DIGITAL TECH INC·Filed 2019·Granted Jun 1, 2021·0 cites·17 claims
- 1152US11960400B2Managing multiple cache memory circuit operationsCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Apr 16, 2024·0 cites·18 claims
- 1252US11086631B2Illegal instruction exception handlingWESTERN DIGITAL TECH INC·Filed 2019·Granted Aug 10, 2021·0 cites·20 claims
- 1352US9286075B2Optimal deallocation of instructions from a unified pick queueSMITTLE MATTHEW B·Filed 2009·Granted Mar 15, 2016·1 cites·20 claims
- 1445US11119149B2Debug command execution using existing datapath circuitryWESTERN DIGITAL TECH INC·Filed 2019·Granted Sep 14, 2021·0 cites·15 claims
- 1544US10430342B2Optimizing thread selection at fetch, select, and commit stages of processor core pipelineORACLE INT CORP·Filed 2015·Granted Oct 1, 2019·0 cites·20 claims
- 1643US10740102B2Hardware mechanism to mitigate stalling of a processor coreORACLE INT CORP·Filed 2017·Granted Aug 11, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →