Inventor · disambiguated record
Yosinori Watanabe
Also filed as: WATANABE YOSINORI
15 granted patents·120 citations·filing 2004–2019
92Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0191US10607039B1Constrained metric optimization of a system on chipCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 31, 2020·15 cites·18 claims
- 0289US9524366B1Annotations to identify objects in design generated by high level synthesis (HLS)CADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 20, 2016·17 cites·20 claims
- 0389US7587687B2System and method for incremental synthesisCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Sep 8, 2009·23 cites·10 claims
- 0488US10133837B1Method and apparatus for converting real number modeling to synthesizable register-transfer level emulation in digital mixed signal environmentsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Nov 20, 2018·10 cites·20 claims
- 0587US10262088B1Converting real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environmentsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 16, 2019·6 cites·20 claims
- 0686US10262095B1Conversion of real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environmentsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 16, 2019·5 cites·20 claims
- 0782US10409939B1Statistical sensitivity analyzerCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 10, 2019·4 cites·20 claims
- 0878US10423741B1Constrained metric verification analysis of a system on chipCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 24, 2019·3 cites·19 claims
- 0977US7363605B1Eliminating false positives in crosstalk noise analysisCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Apr 22, 2008·27 cites·83 claims
- 1073US7472361B2System and method for generating a plurality of models at different levels of abstraction from a single master modelCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Dec 30, 2008·7 cites·19 claims
- 1169US10140202B1Source code annotation for a system on chipCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Nov 27, 2018·1 cites·20 claims
- 1267US11748539B1Converting analog variable delay in real number modeling code to cycle-driven simulation interface codeCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 5, 2023·1 cites·20 claims
- 1358US7673259B2System and method for synthesis reuseCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Mar 2, 2010·1 cites·27 claims
- 1449US11868241B1Method and system for optimizing a verification test regressionCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 9, 2024·0 cites·20 claims
- 1539US8856700B1Methods, systems, and apparatus for reliability synthesisWATANABE YOSINORI·Filed 2008·Granted Oct 7, 2014·0 cites·28 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →