Inventor · disambiguated record
Ravi Varadarajan
Also filed as: VARADARAJAN RAVI
10 granted patents·624 citations·filing 1992–2013
92Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0195US5838583AOptimized placement and routing of datapathsCADENCE DESIGN SYSTEMS INC·Filed 1996·Granted Nov 17, 1998·312 cites·31 claims
- 0287US8839171B1Method of global design closure at top level and driving of downstream implementation flowATRENTA INC·Filed 2013·Granted Sep 16, 2014·26 cites·20 claims
- 0384US5604680AVirtual interface representation of hierarchical symbolic layoutsCADENCE DESIGN SYSTEMS INC·Filed 1994·Granted Feb 18, 1997·106 cites·22 claims
- 0474US7451427B2Bus representation for efficient physical synthesis of integrated circuit designsATRENTA INC·Filed 2006·Granted Nov 11, 2008·7 cites·19 claims
- 0571US8782582B1Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysisATRENTA INC·Filed 2013·Granted Jul 15, 2014·4 cites·22 claims
- 0671US5381343AHier archical pitchmaking compaction method and system for integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 1992·Granted Jan 10, 1995·59 cites·6 claims
- 0768US8732647B1Method for creating physical connections in 3D integrated circuitsATRENTA INC·Filed 2013·Granted May 20, 2014·4 cites·16 claims
- 0867US5281558ACloning method and system for hierarchical compactionCADENCE DESIGN SYSTEMS INC·Filed 1992·Granted Jan 25, 1994·47 cites·12 claims
- 0960US5568396AIdentifying overconstraints using port abstraction graphsCADENCE DESIGN SYSTEMS INC·Filed 1994·Granted Oct 22, 1996·32 cites·15 claims
- 1055US5581474AIdentifying overconstraints using port abstraction graphsCADENCE DESIGN SYSTEMS INC·Filed 1996·Granted Dec 3, 1996·27 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →