Inventor · disambiguated record
Pei-Hsin Ho
Also filed as: HO PEI-HSIN
14 granted patents·1 pending application·296 citations·filing 2001–2024
93Inventor score
Top patents by PatentIndex Score
15 records- 0194US7904867B2Integrating a boolean SAT solver into a routerSYNOPSYS INC·Filed 2007·Granted Mar 8, 2011·53 cites·26 claims
- 0290US7853915B2Interconnect-driven physical synthesis using persistent virtual routingSYNOPSYS INC·Filed 2008·Granted Dec 14, 2010·31 cites·51 claims
- 0389US7546567B2Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chipSYNOPSYS INC·Filed 2007·Granted Jun 9, 2009·29 cites·25 claims
- 0488US7130783B1Simulation-based functional verification of microcircuit designsSYNOPSYS INC·Filed 2001·Granted Oct 31, 2006·66 cites·36 claims
- 0586US8099702B2Method and apparatus for proximate placement of sequential cellsHOU WENTING·Filed 2008·Granted Jan 17, 2012·28 cites·22 claims
- 0685US11194949B1Predictor-guided cell spreader to improve routability for designs at advanced process nodesSYNOPSYS INC·Filed 2018·Granted Dec 7, 2021·7 cites·19 claims
- 0779US7257782B2Method and apparatus for reducing power consumption in an integrated circuit chipSYNOPSYS INC·Filed 2005·Granted Aug 14, 2007·16 cites·24 claims
- 0878US7260802B2Method and apparatus for partitioning an integrated circuit chipSYNOPSYS INC·Filed 2005·Granted Aug 21, 2007·11 cites·20 claims
- 0977US7454727B1Method and Apparatus for Solving Sequential ConstraintsSYNOPSYS INC·Filed 2006·Granted Nov 18, 2008·8 cites·9 claims
- 1077US7076753B2Method and apparatus for solving sequential constraintsSYNOPSYS INC·Filed 2003·Granted Jul 11, 2006·23 cites·17 claims
- 1176US7469392B2Abstraction refinement using controllability and cooperativeness analysisSYNOPSYS INC·Filed 2005·Granted Dec 23, 2008·10 cites·17 claims
- 1269US9141742B2Priori corner and mode reductionSYNOPSYS INC·Filed 2013·Granted Sep 22, 2015·4 cites·6 claims
- 1368US8266563B2Multi-mode redundancy removalPLAZA STEPHEN M·Filed 2009·Granted Sep 11, 2012·8 cites·39 claims
- 1459US7984405B2Method and apparatus for determining the timing of an integrated circuit designSYNOPSYS INC·Filed 2008·Granted Jul 19, 2011·2 cites·29 claims
- 1556US2025068445A1Method and system for emulating a chip design with heterogeneous hardwareSHANGHAI UNIVISTA IND SOFTWARE GROUP CO LTD·Filed 2024·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →