Inventor · disambiguated record
Ravichander Ledalla
Also filed as: LEDALLA RAVICHANDER
7 granted patents·39 citations·filing 2002–2017
80Inventor score
Technology areasG06F
Top patents by PatentIndex Score
7 records- 0191US9342639B1Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertionsIBM·Filed 2015·Granted May 17, 2016·12 cites·16 claims
- 0271US8201120B2Timing point selection for a static timing analysis in the presence of interconnect electrical elementsSOREFF JEFFREY P·Filed 2010·Granted Jun 12, 2012·4 cites·21 claims
- 0371US6763504B2Method for reducing RC parasitics in interconnect networks of an integrated circuitIBM·Filed 2002·Granted Jul 13, 2004·20 cites·10 claims
- 0466US9858383B2Incremental parasitic extraction for coupled timing and power optimizationIBM·Filed 2015·Granted Jan 2, 2018·1 cites·20 claims
- 0564US9607124B2Method of hierarchical timing closure employing dynamic load-sensitive feedback constraintsIBM·Filed 2015·Granted Mar 28, 2017·1 cites·13 claims
- 0658US7870515B2System and method for improved hierarchical analysis of electronic circuitsIBM·Filed 2008·Granted Jan 11, 2011·1 cites·21 claims
- 0753US10169526B2Incremental parasitic extraction for coupled timing and power optimizationIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →