Inventor · disambiguated record
Giap H. Tran
Also filed as: TRAN GIAP · TRAN GIAP H
30 granted patents·1,144 citations·filing 1993–2014
98Inventor score
Top patents by PatentIndex Score
30 records- 0198US6275064B1Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Aug 14, 2001·218 cites·28 claims
- 0297US6249144B1Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resourcesVANTIS CORP·Filed 2000·Granted Jun 19, 2001·67 cites·2 claims
- 0397US6130551ASynthesis-friendly FPGA architecture with variable length and variable timing interconnectVANTIS CORP·Filed 1998·Granted Oct 10, 2000·138 cites·26 claims
- 0496US6380759B1Variable grain architecture for FPGA integrated circuitsVANTIS CORP·Filed 2000·Granted Apr 30, 2002·64 cites·38 claims
- 0596US6097212AVariable grain architecture for FPGA integrated circuitsLATTICE SEMICONDUCTOR CORP·Filed 1997·Granted Aug 1, 2000·105 cites·112 claims
- 0694US7098685B1Scalable serializer-deserializer architecture and programmable interfaceLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Aug 29, 2006·56 cites·20 claims
- 0794US6590415B2Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resourcesLATTICE SEMICONDUCTOR CORP·Filed 2001·Granted Jul 8, 2003·62 cites·13 claims
- 0893US7376037B1Programmable logic device with power-saving architectureLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted May 20, 2008·25 cites·19 claims
- 0993US6216257B1FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocksVANTIS CORP·Filed 2000·Granted Apr 10, 2001·82 cites·10 claims
- 1092US7342838B1Programmable logic device with a double data rate SDRAM interfaceLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Mar 11, 2008·29 cites·11 claims
- 1188US6621298B2Variable grain architecture for FPGA integrated circuitsLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Sep 16, 2003·25 cites·20 claims
- 1288US6154051ATileable and compact layout for super variable grain blocks within FPGA deviceVANTIS CORP·Filed 1998·Granted Nov 28, 2000·75 cites·22 claims
- 1384US6100715AMethods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resourcesVANTIS CORP·Filed 1998·Granted Aug 8, 2000·46 cites·8 claims
- 1473US7558143B1Programmable logic device with power-saving architectureLATTICE SEMICONDUCTOR CORP·Filed 2008·Granted Jul 7, 2009·6 cites·20 claims
- 1573US6526558B2Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resourcesLATTICE SEMICONDUCTOR CORP·Filed 2000·Granted Feb 25, 2003·14 cites·15 claims
- 1671US5990702AFlexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Nov 23, 1999·25 cites·44 claims
- 1770US7787326B1Programmable logic device with a multi-data rate SDRAM interfaceLATTICE SEMICONDUCTOR CORP·Filed 2008·Granted Aug 31, 2010·4 cites·13 claims
- 1867US7061269B1I/O buffer architecture for programmable devicesLATTICE SEMICONDUCTOR CORP·Filed 2004·Granted Jun 13, 2006·13 cites·19 claims
- 1966US6191612B1Enhanced I/O control flexibility for generating control signalsVANTIS CORP·Filed 1998·Granted Feb 20, 2001·20 cites·11 claims
- 2064US9287872B2PVT compensation scheme for output buffersLATTICE SEMICONDUCTOR CORP·Filed 2014·Granted Mar 15, 2016·2 cites·14 claims
- 2161US5982193AInput/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Nov 9, 1999·18 cites·16 claims
- 2255US6292930B1Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resourcesVANTIS CORP·Filed 2000·Granted Sep 18, 2001·7 cites·32 claims
- 2352US6204686B1Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resourcesVANTIS CORP·Filed 1998·Granted Mar 20, 2001·10 cites·33 claims
- 2448US6218857B1Variable sized line driving amplifiers for input/output blocks (IOBs) in FPGA integrated circuitsVANTIS CORP·Filed 1998·Granted Apr 17, 2001·9 cites·13 claims
- 2548US6150842AVariable grain architecture for FPGA integrated circuitsVANTIS CORP·Filed 1999·Granted Nov 21, 2000·6 cites·13 claims
- 2648US6107823AProgrammable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Aug 22, 2000·9 cites·13 claims
- 2741US9515643B2Hot-socket circuitryLATTICE SEMICONDUCTOR CORP·Filed 2014·Granted Dec 6, 2016·0 cites·9 claims
- 2839US5436579AInput transition detection circuit for zero-power partADVANCED MICRO DEVICES INC·Filed 1993·Granted Jul 25, 1995·5 cites·6 claims
- 2937US6124730AMethods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resourcesVANTIS CORP·Filed 1998·Granted Sep 26, 2000·4 cites·10 claims
- 3036US7411419B1Input/output systems and methodsLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Aug 12, 2008·0 cites·16 claims
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