Assignee
VANTIS CORP
US·66 granted patents·2 pending applications·3,389 citations·filing 1997–2001
Top patents by PatentIndex Score
68 records- 0198US6275064B1Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Aug 14, 2001·218 cites·28 claims
- 0297US6284626B1Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trenchVANTIS CORP·Filed 1999·Granted Sep 4, 2001·289 cites·9 claims
- 0397US6249144B1Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resourcesVANTIS CORP·Filed 2000·Granted Jun 19, 2001·67 cites·2 claims
- 0497US6130551ASynthesis-friendly FPGA architecture with variable length and variable timing interconnectVANTIS CORP·Filed 1998·Granted Oct 10, 2000·138 cites·26 claims
- 0597US6102963AElectrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD'sVANTIS CORP·Filed 1997·Granted Aug 15, 2000·175 cites·71 claims
- 0696US6380759B1Variable grain architecture for FPGA integrated circuitsVANTIS CORP·Filed 2000·Granted Apr 30, 2002·64 cites·38 claims
- 0796US6163168AEfficient interconnect network for use in FPGA device having variable grain architectureVANTIS CORP·Filed 1998·Granted Dec 19, 2000·154 cites·31 claims
- 0896US6031365ABand gap reference using a low voltage power supplyVANTIS CORP·Filed 1999·Granted Feb 29, 2000·99 cites·17 claims
- 0995US6214666B1Method of forming a non-volatile memory deviceVANTIS CORP·Filed 1998·Granted Apr 10, 2001·138 cites·16 claims
- 1095US6181163B1FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signalsVANTIS CORP·Filed 1999·Granted Jan 30, 2001·142 cites·17 claims
- 1193US6232631B1Floating gate memory cell structure with programming mechanism outside the read pathVANTIS CORP·Filed 1998·Granted May 15, 2001·107 cites·34 claims
- 1293US6216257B1FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocksVANTIS CORP·Filed 2000·Granted Apr 10, 2001·82 cites·10 claims
- 1393US6064595AFloating gate memory apparatus and method for selected programming thereofVANTIS CORP·Filed 1998·Granted May 16, 2000·123 cites·24 claims
- 1490US6190966B1Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentrationVANTIS CORP·Filed 1997·Granted Feb 20, 2001·76 cites·32 claims
- 1589US6075724AMethod for sorting semiconductor devices having a plurality of non-volatile memory cellsVANTIS CORP·Filed 1999·Granted Jun 13, 2000·73 cites·20 claims
- 1688US6294809B1Avalanche programmed floating gate memory cell structure with program element in polysiliconVANTIS CORP·Filed 1998·Granted Sep 25, 2001·60 cites·28 claims
- 1788US6261944B1Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnectVANTIS CORP·Filed 1998·Granted Jul 17, 2001·93 cites·23 claims
- 1888US6154051ATileable and compact layout for super variable grain blocks within FPGA deviceVANTIS CORP·Filed 1998·Granted Nov 28, 2000·75 cites·22 claims
- 1987US6351157B1Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5 volt) semiconductor processVANTIS CORP·Filed 2000·Granted Feb 26, 2002·34 cites·9 claims
- 2087US6127843ADual port SRAM memory for run time use in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Oct 3, 2000·58 cites·44 claims
- 2187US6028789AZero-power CMOS non-volatile memory cell having an avalanche injection elementVANTIS CORP·Filed 1999·Granted Feb 22, 2000·66 cites·20 claims
- 2286US6128770AConfigurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)VANTIS CORP·Filed 1998·Granted Oct 3, 2000·27 cites·50 claims
- 2386US6034893ANon-volatile memory cell having dual avalanche injection elementsVANTIS CORP·Filed 1999·Granted Mar 7, 2000·61 cites·20 claims
- 2485US6455912B1Process for manufacturing shallow trenches filled with dielectric material having low mechanical stressVANTIS CORP·Filed 2000·Granted Sep 24, 2002·34 cites·15 claims
- 2585US6297128B1Process for manufacturing shallow trenches filled with dielectric material having low mechanical stressVANTIS CORP·Filed 1999·Granted Oct 2, 2001·65 cites·28 claims
- 2684US6211695B1FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sectionsVANTIS CORP·Filed 1999·Granted Apr 3, 2001·41 cites·66 claims
- 2784US6100715AMethods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resourcesVANTIS CORP·Filed 1998·Granted Aug 8, 2000·46 cites·8 claims
- 2883US6274898B1Triple-well EEPROM cell using P-well for tunneling across a channelVANTIS CORP·Filed 1999·Granted Aug 14, 2001·52 cites·20 claims
- 2981US6157568AAvalanche programmed floating gate memory cell structure with program element in first polysilicon layerVANTIS CORP·Filed 1998·Granted Dec 5, 2000·51 cites·29 claims
- 3079US6326663B1Avalanche injection EEPROM memory cell with P-type control gateVANTIS CORP·Filed 1999·Granted Dec 4, 2001·37 cites·23 claims
- 3178US5969992AEEPROM cell using P-well for tunneling across a channelVANTIS CORP·Filed 1998·Granted Oct 19, 1999·42 cites·19 claims
- 3276US6028758AElectrostatic discharge (ESD) protection for a 5.0 volt compatible input/output (I/O) in a 2.5 volt semiconductor processVANTIS CORP·Filed 1998·Granted Feb 22, 2000·38 cites·16 claims
- 3375US6133164AFabrication of oxide regions having multiple thicknesses using minimized number of thermal cyclesVANTIS CORP·Filed 1999·Granted Oct 17, 2000·36 cites·12 claims
- 3474US6294810B1EEPROM cell with tunneling at separate edge and channel regionsVANTIS CORP·Filed 1998·Granted Sep 25, 2001·32 cites·19 claims
- 3574US6133769APhase locked loop with a lock detectorVANTIS CORP·Filed 1998·Granted Oct 17, 2000·37 cites·36 claims
- 3672US6172392B1Boron doped silicon capacitor plateVANTIS CORP·Filed 1999·Granted Jan 9, 2001·28 cites·37 claims
- 3771US6228696B1Semiconductor-oxide-semiconductor capacitor formed in integrated circuitVANTIS CORP·Filed 1998·Granted May 8, 2001·27 cites·22 claims
- 3871US5990702AFlexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Nov 23, 1999·25 cites·44 claims
- 3966US6191612B1Enhanced I/O control flexibility for generating control signalsVANTIS CORP·Filed 1998·Granted Feb 20, 2001·20 cites·11 claims
- 4066US6064105AData retention of EEPROM cell with shallow trench isolation using thicker liner oxideVANTIS CORP·Filed 1998·Granted May 16, 2000·28 cites·3 claims
- 4165US6207989B1Non-volatile memory device having a high-reliability composite insulation layerVANTIS CORP·Filed 1999·Granted Mar 27, 2001·20 cites·18 claims
- 4264US6163175AHigh voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process deviceVANTIS CORP·Filed 1999·Granted Dec 19, 2000·32 cites·11 claims
- 4362US5912550APower converter with 2.5 volt semiconductor process componentsVANTIS CORP·Filed 1998·Granted Jun 15, 1999·17 cites·17 claims
- 4461US5982193AInput/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuitsVANTIS CORP·Filed 1997·Granted Nov 9, 1999·18 cites·16 claims
- 4559US6097664AMulti-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scanVANTIS CORP·Filed 1999·Granted Aug 1, 2000·18 cites·32 claims
- 4656US6215700B1PMOS avalanche programmed floating gate memory cell structureVANTIS CORP·Filed 1999·Granted Apr 10, 2001·16 cites·24 claims
- 4755US6292930B1Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resourcesVANTIS CORP·Filed 2000·Granted Sep 18, 2001·7 cites·32 claims
- 4855US6169432B1High voltage switch for providing voltages higher than 2.5 volts with transistors made using a 2.5 volt processVANTIS CORP·Filed 1998·Granted Jan 2, 2001·13 cites·8 claims
- 4955US5999449ATwo transistor EEPROM cell using P-well for tunneling across a channelVANTIS CORP·Filed 1999·Granted Dec 7, 1999·15 cites·21 claims
- 5054US6091595AElectrostatic discharge (ESD) protection for NMOS pull up transistors of a 5.0 volt compatible output buffer using 2.5 volt process transistorsVANTIS CORP·Filed 1998·Granted Jul 18, 2000·14 cites·4 claims
Showing the top 50 of 68 patent records by PatentIndex Score.
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