Inventor · disambiguated record
Daniel Mark Nelson
Also filed as: NELSON DANIEL M · NELSON DANIEL MARK
26 granted patents·5 pending applications·173 citations·filing 2005–2015
96Inventor score
Files withIBM21BEHRENDS DERICK G4BEHRENDS DERICK GARDNER3ADAMS CHAD A1AVAGO TECHNOLOGIES GENERAL IP1
Top patents by PatentIndex Score
31 records- 0195US8279687B2Single supply sub VDD bit-line precharge SRAM and method for level shiftingADAMS CHAD A·Filed 2010·Granted Oct 2, 2012·31 cites·20 claims
- 0292US8520429B2Data dependent SRAM write assistBEHRENDS DERICK G·Filed 2011·Granted Aug 27, 2013·18 cites·2 claims
- 0389US8159260B1Delay chain burn-in for increased repeatability of physically unclonable functionsBEHRENDS DERICK GARDNER·Filed 2010·Granted Apr 17, 2012·15 cites·13 claims
- 0484US7535776B1Circuit for improved SRAM write around with reduced read access penaltyIBM·Filed 2008·Granted May 19, 2009·16 cites·1 claims
- 0584US7502276B1Method and apparatus for multi-word write in domino read SRAMsIBM·Filed 2008·Granted Mar 10, 2009·15 cites·1 claims
- 0682US7924633B2Implementing boosted wordline voltage in memoriesIBM·Filed 2009·Granted Apr 12, 2011·13 cites·17 claims
- 0782US7505340B1Method for implementing SRAM cell write performance evaluationIBM·Filed 2007·Granted Mar 17, 2009·10 cites·6 claims
- 0879US7737757B2Low power level shifting latch circuits with gated feedback for high speed integrated circuitsIBM·Filed 2008·Granted Jun 15, 2010·9 cites·15 claims
- 0974US9959926B2Method and apparatus for selective write assist using shared boost capacitorAVAGO TECHNOLOGIES GENERAL IP·Filed 2015·Granted May 1, 2018·4 cites·20 claims
- 1073US7724586B2Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usageIBM·Filed 2008·Granted May 25, 2010·8 cites·18 claims
- 1171US8711606B2Data security for dynamic random access memory using body bias to clear data at power-upIBM·Filed 2013·Granted Apr 29, 2014·3 cites·9 claims
- 1265US8344782B2Method and apparatus to limit circuit delay dependence on voltage for single phase transitionIBM·Filed 2009·Granted Jan 1, 2013·4 cites·17 claims
- 1363US7443744B2Method for reducing wiring and required number of redundant elementsIBM·Filed 2006·Granted Oct 28, 2008·4 cites·4 claims
- 1461US8467230B2Data security for dynamic random access memory using body bias to clear data at power-upBEHRENDS DERICK GARDNER·Filed 2010·Granted Jun 18, 2013·2 cites·6 claims
- 1561US7788554B2Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluationIBM·Filed 2007·Granted Aug 31, 2010·3 cites·16 claims
- 1660US8675427B2Implementing RC and coupling delay correction for SRAMBEHRENDS DERICK G·Filed 2012·Granted Mar 18, 2014·2 cites·20 claims
- 1760US7724585B2Implementing local evaluation of domino read SRAM with enhanced SRAM cell stabilityIBM·Filed 2008·Granted May 25, 2010·4 cites·18 claims
- 1859US8395963B2Data security for dynamic random access memory at power-upBEHRENDS DERICK G·Filed 2010·Granted Mar 12, 2013·2 cites·11 claims
- 1957US7911827B2Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levelsIBM·Filed 2009·Granted Mar 22, 2011·3 cites·18 claims
- 2057US7751266B2High performance read bypass test for SRAM circuitsIBM·Filed 2008·Granted Jul 6, 2010·3 cites·18 claims
- 2155US9142560B2Layout to minimize FET variation in small dimension photolithographyIBM·Filed 2014·Granted Sep 22, 2015·0 cites·3 claims
- 2255US7714630B2Method and apparatus to limit circuit delay dependence on voltageIBM·Filed 2008·Granted May 11, 2010·2 cites·1 claims
- 2354US8824196B2Single cycle data copy for two-port SRAMBEHRENDS DERICK G·Filed 2012·Granted Sep 2, 2014·1 cites·21 claims
- 2451US7971164B2Assessing resources required to complete a VLSI designIBM·Filed 2008·Granted Jun 28, 2011·0 cites·20 claims
- 2549US7768851B2Apparatus for implementing SRAM cell write performance evaluationIBM·Filed 2009·Granted Aug 3, 2010·1 cites·13 claims
- 2648US2010030804A1Synchronization of Locations in Real and Virtual WorldsIBM·Filed 2008·Application pending·0 cites
- 2747US8860141B2Layout to minimize FET variation in small dimension photolithographyBEHRENDS DERICK GARDNER·Filed 2012·Granted Oct 14, 2014·0 cites·3 claims
- 2840US2008273406A1Enhanced sram redundancy circuit for reducing wiring and required number of redundant elementsIBM·Filed 2008·Application pending·0 cites
- 2936US2008112219A1Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and Required Number of Redundant ElementsIBM·Filed 2007·Application pending·0 cites
- 3035US2015262667A1Low power hit bitline driver for content-addressable memoryLSI CORP·Filed 2014·Application pending·0 cites
- 3133US2007047282A1Method and apparatus for implementing power saving for content addressable memoryIBM·Filed 2005·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Daniel Mark Nelson files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →