Inventor · disambiguated record
Noriko Shinomiya
Also filed as: SHINOMIYA NORIKO
9 granted patents·1 pending application·427 citations·filing 1995–2007
90Inventor score
Top patents by PatentIndex Score
10 records- 0189US5852562AMethod and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zonesMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1995·Granted Dec 22, 1998·180 cites·6 claims
- 0288US6330707B1Automatic routing methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1998·Granted Dec 11, 2001·155 cites·13 claims
- 0382US8024689B2Semiconductor integrated circuit apparatus with low wiring resistancePANASONIC CORP·Filed 2007·Granted Sep 20, 2011·12 cites·17 claims
- 0457US7441214B2Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording mediaMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2006·Granted Oct 21, 2008·1 cites·15 claims
- 0557US7139989B2Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording mediaMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Nov 21, 2006·5 cites·10 claims
- 0657US6560759B2Semiconductor integrated circuit device, design method for the same and computer-readable recording where medium I/O cell library is recordedMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2001·Granted May 6, 2003·8 cites·20 claims
- 0753US5943486ACompaction method, compaction apparatus, routing method and routing apparatusMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1996·Granted Aug 24, 1999·28 cites·22 claims
- 0852US6336207B2Method and apparatus for designing LSI layout, cell library for designing LSI layout and semiconductor integrated circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1998·Granted Jan 1, 2002·26 cites·19 claims
- 0941US2006038201A1Layout symmetry constraint checking method and layout symmetry constraint checking apparatusSHINOMIYA NORIKO·Filed 2005·Application pending·0 cites
- 1039US6202195B1Semiconductor integrated circuit layout methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1997·Granted Mar 13, 2001·12 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →