Inventor · disambiguated record
Evanthia Papadopoulou
Also filed as: PAPADOPOULOU EVANTHIA
16 granted patents·2 pending applications·442 citations·filing 1998–2008
93Inventor score
Top patents by PatentIndex Score
18 records- 0190US6317859B1Method and system for determining critical area for circuit layoutsIBM·Filed 1999·Granted Nov 13, 2001·168 cites·39 claims
- 0288US6247853B1Incremental method for critical area and critical region computation of via blocksIBM·Filed 1998·Granted Jun 19, 2001·100 cites·14 claims
- 0386US6178539B1Method and system for determining critical area for circuit layouts using voronoi diagramsIBM·Filed 1998·Granted Jan 23, 2001·87 cites·36 claims
- 0475US7240306B2Integrated circuit layout critical area determination using Voronoi diagrams and shape biasingIBM·Filed 2005·Granted Jul 3, 2007·8 cites·20 claims
- 0574US7143371B2Critical area computation of composite fault mechanisms using voronoi diagramsIBM·Filed 2004·Granted Nov 28, 2006·16 cites·9 claims
- 0672US6044208AIncremental critical area computation for VLSI yield predictionIBM·Filed 1998·Granted Mar 28, 2000·40 cites·10 claims
- 0771US7404159B2Critical area computation of composite fault mechanisms using Voronoi diagramsIBM·Filed 2006·Granted Jul 22, 2008·4 cites·13 claims
- 0869US7404164B2IC design modeling allowing dimension-dependent rule checkingIBM·Filed 2004·Granted Jul 22, 2008·10 cites·7 claims
- 0967US7661080B2Method and apparatus for net-aware critical area extractionIBM·Filed 2007·Granted Feb 9, 2010·4 cites·30 claims
- 1066US7703061B2IC design modeling allowing dimension-dependent rule checkingIBM·Filed 2008·Granted Apr 20, 2010·2 cites·15 claims
- 1162US7555735B2IC design modeling allowing dimension-dependent rule checkingIBM·Filed 2007·Granted Jun 30, 2009·1 cites·13 claims
- 1261US7685553B2System and method for global circuit routing incorporating estimation of critical area estimate metricsIBM·Filed 2007·Granted Mar 23, 2010·2 cites·34 claims
- 1354US7810060B2Critical area computation of composite fault mechanisms using Voronoi diagramsIBM·Filed 2008·Granted Oct 5, 2010·0 cites·7 claims
- 1454US7577927B2IC design modeling allowing dimension-dependent rule checkingIBM·Filed 2008·Granted Aug 18, 2009·0 cites·12 claims
- 1549US7752580B2Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing techniqueIBM·Filed 2007·Granted Jul 6, 2010·0 cites·20 claims
- 1648US7752589B2Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit designIBM·Filed 2007·Granted Jul 6, 2010·0 cites·32 claims
- 1745US2009125852A1Method and apparatus for net-aware critical area extractionPAPADOPOULOU EVANTHIA·Filed 2007·Application pending·0 cites
- 1837US2005202326A1Optimized placement of sub-resolution assist features within two-dimensional environmentsIBM·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →