Inventor · disambiguated record
David Keppel
Also filed as: KEPPEL DAVID · KEPPEL DAVID P · KEPPEL DAVID PARDO
39 granted patents·7 pending applications·630 citations·filing 1997–2023
97Inventor score
Top patents by PatentIndex Score
46 records- 0195US9342403B2Method and apparatus for managing a spin transfer torque memoryINTEL CORP·Filed 2014·Granted May 17, 2016·32 cites·32 claims
- 0289US11055232B2Valid bits of a translation lookaside buffer (TLB) for checking multiple page sizes in one probe cycle and reconfigurable sub-TLBSINTEL CORP·Filed 2019·Granted Jul 6, 2021·6 cites·20 claims
- 0386US5905855AMethod and apparatus for correcting errors in computer systemsTRANSMETA CORP·Filed 1997·Granted May 18, 1999·140 cites·23 claims
- 0484US9116729B2Handling of binary translated self modifying code and cross modifying codeINTEL CORP·Filed 2012·Granted Aug 25, 2015·10 cites·24 claims
- 0583US6738892B1Use of enable bits to control execution of selected instructionsTRANSMETA CORP·Filed 1999·Granted May 18, 2004·106 cites·15 claims
- 0681US9477628B2Collective communications apparatus and method for parallel systemsINTEL CORP·Filed 2013·Granted Oct 25, 2016·6 cites·25 claims
- 0780US10135708B2Technologies for performance inspection at an endpoint nodeINTEL CORP·Filed 2015·Granted Nov 20, 2018·4 cites·25 claims
- 0878US10409763B2Apparatus and method for efficiently implementing a processor pipelineINTEL CORP·Filed 2014·Granted Sep 10, 2019·6 cites·8 claims
- 0977US9971599B2Instruction and logic for support of code modificationINTEL CORP·Filed 2017·Granted May 15, 2018·2 cites·20 claims
- 1072US7640450B1Method and apparatus for handling nested faultsANVIN H PETER·Filed 2004·Granted Dec 29, 2009·14 cites·19 claims
- 1171US6363336B1Fine grain translation discriminationTRANSMETA CORP·Filed 1999·Granted Mar 26, 2002·63 cites·19 claims
- 1270US6415379B1Method and apparatus for maintaining context while executing translated instructionsTRANSMETA CORP·Filed 1999·Granted Jul 2, 2002·57 cites·12 claims
- 1369US9442849B2Apparatus and method for reduced core entry into a power state having a powered down core cacheINTEL CORP·Filed 2012·Granted Sep 13, 2016·2 cites·20 claims
- 1469US6356615B1Programmable event counter systemTRANSMETA CORP·Filed 1999·Granted Mar 12, 2002·57 cites·17 claims
- 1568US12405727B2Method and apparatus for data buffering of write operations and performing write operationsINTEL CORP·Filed 2023·Granted Sep 2, 2025·0 cites·20 claims
- 1664US10135711B2Technologies for sideband performance tracing of network trafficINTEL CORP·Filed 2015·Granted Nov 20, 2018·1 cites·25 claims
- 1763US10061376B2Opportunistic power management for managing intermittent power available to data processing device having semi-non-volatile memory or non-volatile memoryINTEL CORP·Filed 2015·Granted Aug 28, 2018·1 cites·19 claims
- 1863US9766685B2Controlling power consumption of a processor using interrupt-mediated on-off keyingINTEL CORP·Filed 2013·Granted Sep 19, 2017·1 cites·19 claims
- 1961US6829719B2Method and apparatus for handling nested faultsTRANSMETA CORP·Filed 2001·Granted Dec 7, 2004·6 cites·14 claims
- 2061US6668287B1Software direct memory accessTRANSMETA CORP·Filed 1999·Granted Dec 23, 2003·39 cites·20 claims
- 2158US12438960B2Metadata compaction in packet coalescingINTEL CORP·Filed 2022·Granted Oct 7, 2025·0 cites·20 claims
- 2258US6714904B1System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructionsTRANSMETA CORP·Filed 1999·Granted Mar 30, 2004·33 cites·20 claims
- 2357US7617088B1Interpage prologue to protect virtual address mappingsBEDICHEK ROBERT·Filed 2005·Granted Nov 10, 2009·1 cites·11 claims
- 2455US10168765B2Controlling processor consumption using on-off keying having a maxiumum off timeINTEL CORP·Filed 2016·Granted Jan 1, 2019·0 cites·20 claims
- 2554US9965023B2Apparatus and method for flushing dirty cache lines based on cache activity levelsINTEL CORP·Filed 2016·Granted May 8, 2018·0 cites·25 claims
- 2654US9354694B2Controlling processor consumption using on-off keying having a maximum off timeINTEL CORP·Filed 2013·Granted May 31, 2016·0 cites·17 claims
- 2754US8418153B2Method for integration of interpretation and translation in a microprocessorBEDICHEK ROBERT·Filed 2009·Granted Apr 9, 2013·0 cites·21 claims
- 2851US10061587B2Instruction and logic for bulk register reclamationINTEL CORP·Filed 2014·Granted Aug 28, 2018·0 cites·20 claims
- 2951US2024126680A1Apparatuses, Devices, Methods and Computer Programs for Allocating MemoryKEPPEL DAVID·Filed 2023·Application pending·0 cites
- 3050US12242753B2Reduced network load with combined put or get and receiver-managed offsetINTEL CORP·Filed 2021·Granted Mar 4, 2025·0 cites·20 claims
- 3149US10771404B2Performance monitoringINTEL CORP·Filed 2016·Granted Sep 8, 2020·0 cites·25 claims
- 3249US9652268B2Instruction and logic for support of code modificationKELM JOHN H·Filed 2014·Granted May 16, 2017·0 cites·20 claims
- 3348US11989135B2Programmable address range engine for larger region sizesINTEL CORP·Filed 2020·Granted May 21, 2024·0 cites·15 claims
- 3448US9329658B2Block-level sleep logicINTEL CORP·Filed 2012·Granted May 3, 2016·0 cites·23 claims
- 3547US10331550B2Symmetric addressingINTEL CORP·Filed 2016·Granted Jun 25, 2019·0 cites·19 claims
- 3646US6845353B1Interpage prologue to protect virtual address mappingsTRANSMETA CORP·Filed 1999·Granted Jan 18, 2005·15 cites·14 claims
- 3746US6513110B1Check instruction and methodTRANSMETA CORP·Filed 1999·Granted Jan 28, 2003·17 cites·13 claims
- 3846US2016179662A1Instruction and logic for page table walk change-bitsKEPPEL DAVID PARDO·Filed 2014·Application pending·0 cites
- 3945US10200310B2Fabric-integrated data pulling engineINTEL CORP·Filed 2015·Granted Feb 5, 2019·0 cites·26 claims
- 4045US2022206955A1Automated translation lookaside buffer set rebalancingINTEL CORP·Filed 2020·Application pending·0 cites
- 4142US2022107897A1Cache probe transaction filteringINTEL CORP·Filed 2021·Application pending·0 cites
- 4240US10178041B2Technologies for aggregation-based message synchronizationINTEL CORP·Filed 2015·Granted Jan 8, 2019·0 cites·21 claims
- 4339US7761857B1Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution countsBEDICHEK ROBERT·Filed 1999·Granted Jul 20, 2010·11 cites·26 claims
- 4436US2017289242A1Technologies for dynamic work queue managementKEPPEL DAVID·Filed 2016·Application pending·0 cites
- 4536US2017187587A1Technologies for inline network traffic performance tracingKEPPEL DAVID·Filed 2015·Application pending·0 cites
- 4635US2016283247A1Apparatuses and methods to selectively execute a commit instructionINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →