Inventor · disambiguated record
Cliff Kucharski
Also filed as: Kucharski Cliff
23 granted patents·1 pending application·21 citations·filing 2015–2022
91Inventor score
Technology areasG06F
Files withIBM24
Top patents by PatentIndex Score
24 records- 0189US11941398B1Fast mapper restore for flush in processorIBM·Filed 2022·Granted Mar 26, 2024·1 cites·20 claims
- 0287US9740620B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 22, 2017·5 cites·13 claims
- 0386US10073699B2Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architectureIBM·Filed 2015·Granted Sep 11, 2018·5 cites·20 claims
- 0484US9639418B2Parity protection of a registerIBM·Filed 2015·Granted May 2, 2017·4 cites·20 claims
- 0582US9747217B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 29, 2017·3 cites·7 claims
- 0671US11144364B2Supporting speculative microprocessor instruction executionIBM·Filed 2019·Granted Oct 12, 2021·1 cites·18 claims
- 0771US10949205B2Implementation of execution compression of instructions in slice target register file mapperIBM·Filed 2018·Granted Mar 16, 2021·1 cites·20 claims
- 0865US10255071B2Method and apparatus for managing a speculative transaction in a processing unitIBM·Filed 2015·Granted Apr 9, 2019·1 cites·20 claims
- 0961US11138050B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2019·Granted Oct 5, 2021·0 cites·20 claims
- 1056US11093282B2Register file write using pointersIBM·Filed 2019·Granted Aug 17, 2021·0 cites·17 claims
- 1155US11768684B2Compaction of architected registers in a simultaneous multithreading processorIBM·Filed 2020·Granted Sep 26, 2023·0 cites·17 claims
- 1253US10248421B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2016·Granted Apr 2, 2019·0 cites·6 claims
- 1353US10241790B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2015·Granted Mar 26, 2019·0 cites·12 claims
- 1451US11194578B2Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessorIBM·Filed 2018·Granted Dec 7, 2021·0 cites·18 claims
- 1551US10489253B2On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessorIBM·Filed 2017·Granted Nov 26, 2019·0 cites·20 claims
- 1651US10318356B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2016·Granted Jun 11, 2019·0 cites·12 claims
- 1749US11561794B2Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entryIBM·Filed 2021·Granted Jan 24, 2023·0 cites·20 claims
- 1849US10649779B2Variable latency pipe for interleaving instruction tags in a microprocessorIBM·Filed 2016·Granted May 12, 2020·0 cites·7 claims
- 1948US11188332B2System and handling of register data in processorsIBM·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 2048US10282205B2Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructionsIBM·Filed 2015·Granted May 7, 2019·0 cites·20 claims
- 2147US11030018B2On-demand multi-tiered hang buster for SMT microprocessorIBM·Filed 2017·Granted Jun 8, 2021·0 cites·18 claims
- 2247US10613868B2Variable latency pipe for interleaving instruction tags in a microprocessorIBM·Filed 2015·Granted Apr 7, 2020·0 cites·11 claims
- 2345US10289415B2Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register dataIBM·Filed 2015·Granted May 14, 2019·0 cites·20 claims
- 2444US2020019405A1Multiple Level History Buffer for Transaction Memory SupportIBM·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →