Inventor · disambiguated record
Donald L. Sollars
Also filed as: SOLLARS DONALD · SOLLARS DONALD L
20 granted patents·2 pending applications·601 citations·filing 1989–2017
96Inventor score
Top patents by PatentIndex Score
22 records- 0195US5021684AProcess, supply, temperature compensating CMOS output bufferINTEL CORP·Filed 1989·Granted Jun 4, 1991·77 cites·11 claims
- 0289US10253511B2Multi-flex forming systemSOLLARS DONALD·Filed 2017·Granted Apr 9, 2019·4 cites·17 claims
- 0389US6178482B1Virtual register setsBRECIS COMM·Filed 1997·Granted Jan 23, 2001·165 cites·17 claims
- 0481US5376829AHigh-speed complementary multiplexerSUN MICROSYSTEMS INC·Filed 1993·Granted Dec 27, 1994·36 cites·8 claims
- 0580US8651450B2Adjustable and reusable brace, kicker and tie apparatusSOLLARS DONALD·Filed 2010·Granted Feb 18, 2014·7 cites·18 claims
- 0680US5900025AProcessor having a hierarchical control register file and methods for operating the sameZSP CORP·Filed 1995·Granted May 4, 1999·104 cites·20 claims
- 0767US6505291B1Processor having a datapath and control logic constituted with basis execution blocksBRECIS COMM·Filed 2000·Granted Jan 7, 2003·11 cites·3 claims
- 0864US6081880AProcessor having a scalable, uni/multi-dimensional, and virtually/physically addressed operand register fileLSI LOGIC CORP·Filed 1995·Granted Jun 27, 2000·45 cites·28 claims
- 0962US8931753B2Adjustable form panel system and method of formingSOLLARS DONALD·Filed 2010·Granted Jan 13, 2015·2 cites·27 claims
- 1054US6016539ADatapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operationsTERAGEN CORP·Filed 1997·Granted Jan 18, 2000·25 cites·13 claims
- 1151US6438679B1Multiple ISA support by a processor using primitive operationsBRECIS COMM·Filed 1998·Granted Aug 20, 2002·24 cites·31 claims
- 1251US5966529AProcessor having auxiliary operand register file and complementary arrangements for non-disruptively performing adjunct executionZSP CORP·Filed 1995·Granted Oct 12, 1999·27 cites·40 claims
- 1342US6327632B1Adaptable I/O pins manifesting I/O characteristics responsive to bit values stored in selected addressable storage locations, each pin coupled to three corresponding addressable storage locationsBRECIS COMM·Filed 1999·Granted Dec 4, 2001·12 cites·19 claims
- 1441US2010218438A1Adjustable and/or reusable brace and kicker method and apparatusSOLLARS DONALD·Filed 2010·Application pending·0 cites
- 1540US6216218B1Processor having a datapath and control logic constituted with basis execution blocksFiled 1998·Granted Apr 10, 2001·10 cites·8 claims
- 1640US5940626AProcessor having an instruction set architecture implemented with hierarchically organized primitive operationsTERAGEN CORP·Filed 1997·Granted Aug 17, 1999·13 cites·18 claims
- 1740US5923894AAdaptable input/output pin controlTERAGEN CORP·Filed 1997·Granted Jul 13, 1999·11 cites·38 claims
- 1837US2009158876A1Modular gear teeth and gears employing sameSOLLARS MERLE L·Filed 2007·Application pending·0 cites
- 1936US5799164AMethod and apparatus for prefetching instructions at an improved rate based on dispatched control transfer instruction statesSUN MICROSYSTEMS INC·Filed 1997·Granted Aug 25, 1998·8 cites·20 claims
- 2035US6067601ACache memory based instruction executionBRECIS COMMUNICATIONS·Filed 1997·Granted May 23, 2000·12 cites·49 claims
- 2133US6308254B1Processing instructions of an instruction set architecture by executing hierarchically organized snippets of atomic units of primitive operationsBRECIS·Filed 1999·Granted Oct 23, 2001·8 cites·16 claims
- 2230US6260112B1Register memory linkingLSI LOGIC CORP·Filed 1998·Granted Jul 10, 2001·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →