Inventor · disambiguated record
Wee Liew
Also filed as: LIEW WEE · LIEW WEE K · LIEW WEE KEONG
8 granted patents·3 pending applications·164 citations·filing 2001–2020
87Inventor score
Top patents by PatentIndex Score
11 records- 0194US6608376B1Integrated circuit package substrate with high density routing mechanismLSI LOGIC CORP·Filed 2002·Granted Aug 19, 2003·81 cites·21 claims
- 0278US6897555B1Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit dieLSI LOGIC CORP·Filed 2003·Granted May 24, 2005·32 cites·26 claims
- 0371US6525421B1Molded integrated circuit packageLSI LOGIC CORP·Filed 2001·Granted Feb 25, 2003·18 cites·5 claims
- 0468US6512293B1Mechanically interlocking ball grid array packages and method of makingLSI LOGIC CORP·Filed 2001·Granted Jan 28, 2003·15 cites·11 claims
- 0560US6687133B1Ground plane on 2 layer PBGALSI LOGIC CORP·Filed 2002·Granted Feb 3, 2004·11 cites·3 claims
- 0650US6566167B1PBGA electrical noise isolation of signal tracesLSI LOGIC CORP·Filed 2001·Granted May 20, 2003·4 cites·12 claims
- 0749US12182047B2Chip-to-chip interface of a multi-chip module (MCM)INTEL CORP·Filed 2020·Granted Dec 31, 2024·0 cites·28 claims
- 0848US6825554B2PBGA electrical noise isolation of signal tracesLSI LOGIC CORP·Filed 2003·Granted Nov 30, 2004·3 cites·5 claims
- 0938US2006065983A1Semiconductor package with wire bond arrangement to reduce cross talk for high speed circuitsLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 1038US2006043565A1Laser removal of plating tails for high speed packagesCHIA CHOK J·Filed 2004·Application pending·0 cites
- 1134US2006043587A1Apparatus and method for reducing signal cross talk between wire bonds of semiconductor packagesLSI LOGIC CORP A DELAWARE CORP·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →