Inventor · disambiguated record
Karim M. Abdalla
Also filed as: ABDALLA KARIM · ABDALLA KARIM M · ABDALLA KARIM MAHER
33 granted patents·426 citations·filing 1996–2015
97Inventor score
Top patents by PatentIndex Score
33 records- 0194US7802118B1Functional block level clock-gating within a graphics processorNVIDIA CORP·Filed 2006·Granted Sep 21, 2010·45 cites·1 claims
- 0293US6535209B1Data stream splitting and storage in graphics data processingNVIDIA US INVEST CO·Filed 2000·Granted Mar 18, 2003·114 cites·16 claims
- 0392US7797561B1Automatic functional block level clock-gatingNVIDIA CORP·Filed 2006·Granted Sep 14, 2010·36 cites·6 claims
- 0489US10217183B2System, method, and computer program product for simultaneous execution of compute and graphics workloadsNVIDIA CORP·Filed 2013·Granted Feb 26, 2019·12 cites·19 claims
- 0587US7649538B1Reconfigurable high performance texture pipeline with advanced filteringNVIDIA CORP·Filed 2006·Granted Jan 19, 2010·16 cites·20 claims
- 0686US7218291B2Increased scalability in the fragment shading pipelineNVIDIA CORP·Filed 2004·Granted May 15, 2007·43 cites·27 claims
- 0785US9594599B1Method and system for distributing work batches to processing units based on a number of enabled streaming multiprocessorsJOHNSON PHILIP BROWNING·Filed 2009·Granted Mar 14, 2017·15 cites·12 claims
- 0885US7916149B1Block linear memory ordering of texture dataNVIDIA CORP·Filed 2005·Granted Mar 29, 2011·11 cites·17 claims
- 0984US7884831B2Reconfigurable high-performance texture pipeline with advanced filteringNVIDIA CORP·Filed 2010·Granted Feb 8, 2011·4 cites·20 claims
- 1083US9069609B2Scheduling and execution of compute tasksABDALLA KARIM M·Filed 2012·Granted Jun 30, 2015·9 cites·22 claims
- 1176US9507638B2Compute work distribution reference countersCUADRA PHILIP ALEXANDER·Filed 2011·Granted Nov 29, 2016·5 cites·20 claims
- 1276US7385607B2Scalable shader architectureNVIDIA CORP·Filed 2004·Granted Jun 10, 2008·19 cites·44 claims
- 1375US9639366B2Techniques for managing graphics processing resources in a tile-based architectureNVIDIA CORP·Filed 2013·Granted May 2, 2017·1 cites·20 claims
- 1475US8984183B2Signaling, ordering, and execution of dynamically generated tasks in a processing systemPURCELL TIMOTHY JOHN·Filed 2011·Granted Mar 17, 2015·4 cites·19 claims
- 1574US9715413B2Execution state analysis for assigning tasks to streaming multiprocessorsABDALLA KARIM M·Filed 2012·Granted Jul 25, 2017·4 cites·22 claims
- 1673US8917271B2Redistribution of generated geometric primitivesRHOADES JOHNNY S·Filed 2010·Granted Dec 23, 2014·4 cites·24 claims
- 1772US7852340B2Scalable shader architectureNVIDIA CORP·Filed 2007·Granted Dec 14, 2010·5 cites·16 claims
- 1871US9792122B2Heuristics for improving performance in a tile based architectureNVIDIA CORP·Filed 2013·Granted Oct 17, 2017·0 cites·22 claims
- 1969US8223150B2Translation of register-combiner state into shader microcodeCABRAL BRIAN·Filed 2011·Granted Jul 17, 2012·2 cites·20 claims
- 2068US10332310B2Distributed index fetch, primitive assembly, and primitive batchingNVIDIA CORP·Filed 2015·Granted Jun 25, 2019·2 cites·20 claims
- 2168US9710306B2Methods and apparatus for auto-throttling encapsulated compute tasksDULUK JR JEROME F·Filed 2012·Granted Jul 18, 2017·2 cites·22 claims
- 2268US8004523B1Translation of register-combiner state into shader microcodeNVIDIA CORP·Filed 2007·Granted Aug 23, 2011·3 cites·19 claims
- 2367US7542042B1Subpicture overlay using fragment shaderNVIDIA CORP·Filed 2004·Granted Jun 2, 2009·9 cites·14 claims
- 2467US7490208B1Architecture for compact multi-ported register fileNVIDIA CORP·Filed 2004·Granted Feb 10, 2009·12 cites·23 claims
- 2566US7576751B2Pixel center position displacementNVIDIA CORP·Filed 2006·Granted Aug 18, 2009·3 cites·16 claims
- 2663US9436969B2Time slice processing of tessellation and geometry shadersHAKURA ZIYAD S·Filed 2011·Granted Sep 6, 2016·2 cites·26 claims
- 2763US8456481B2Block linear memory ordering of texture data techniquesDONOVAN WALTER E·Filed 2012·Granted Jun 4, 2013·1 cites·11 claims
- 2863US8436868B2Block linear memory ordering of texture dataDONOVAN WALTER E·Filed 2011·Granted May 7, 2013·1 cites·8 claims
- 2963US7821520B1Fragment processor having dual mode register fileNVIDIA CORP·Filed 2004·Granted Oct 26, 2010·9 cites·26 claims
- 3061US7425966B2Pixel center position displacementNVIDIA CORP·Filed 2004·Granted Sep 16, 2008·7 cites·18 claims
- 3157US9921873B2Controlling work distribution for processing tasksSHAH LACKY V·Filed 2012·Granted Mar 20, 2018·1 cites·18 claims
- 3252US7369135B2Memory management system having a forward progress bitNVIDIA CORP·Filed 2004·Granted May 6, 2008·2 cites·16 claims
- 3348US6154794AUpstream situated apparatus and method within a computer system for controlling data flow to a downstream situated input/output unitSILICON GRAPHICS INC·Filed 1996·Granted Nov 28, 2000·23 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Karim M. Abdalla files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →