Inventor · disambiguated record
Seongmoon Wang
Also filed as: WANG SEONGMOON
17 granted patents·4 pending applications·211 citations·filing 2001–2009
94Inventor score
Top patents by PatentIndex Score
21 records- 0193US7484151B2Method and apparatus for testing logic circuit designsNEC LAB AMERICA INC·Filed 2006·Granted Jan 27, 2009·22 cites·8 claims
- 0291US7610527B2Test output compaction with improved blocking of unknown valuesNEC LAB AMERICA INC·Filed 2006·Granted Oct 27, 2009·22 cites·15 claims
- 0389US7610540B2Method for generating, from a test cube set, a generator configured to generate a test patternNEC LAB AMERICA INC·Filed 2008·Granted Oct 27, 2009·14 cites·11 claims
- 0488US7131081B2Scalable scan-path test point insertion techniqueNEC LAB AMERICA INC·Filed 2003·Granted Oct 31, 2006·36 cites·38 claims
- 0587US7610539B2Method and apparatus for testing logic circuit designsNEC LAB AMERICA INC·Filed 2008·Granted Oct 27, 2009·12 cites·9 claims
- 0675US6886124B2Low hardware overhead scan based 3-weight weighted random BIST architecturesNEC CORP·Filed 2001·Granted Apr 26, 2005·22 cites·35 claims
- 0774US7562321B2Method and apparatus for structured ASIC test point insertionNEC LAB AMERICA INC·Filed 2006·Granted Jul 14, 2009·7 cites·25 claims
- 0874US7302626B2Test pattern compression with pattern-independent design-independent seed compressionNEC LAB AMERICA INC·Filed 2005·Granted Nov 27, 2007·7 cites·11 claims
- 0969US7284176B2Externally-loaded weighted random test pattern compressionNEC LAB AMERICA INC·Filed 2004·Granted Oct 16, 2007·13 cites·20 claims
- 1069US7222277B2Test output compaction using response shaperNEC LAB AMERICA INC·Filed 2004·Granted May 22, 2007·14 cites·16 claims
- 1168US8214172B2Systems and methods for locating defective components of a circuitWANG SEONGMOON·Filed 2009·Granted Jul 3, 2012·7 cites·5 claims
- 1267US7313746B2Test output compaction for responses with unknown valuesNEC LAB AMERICA INC·Filed 2006·Granted Dec 25, 2007·5 cites·16 claims
- 1364US7188323B2Restricted scan reordering technique to enhance delay fault coverageNEC LAB AMERICA INC·Filed 2004·Granted Mar 6, 2007·10 cites·18 claims
- 1463US7730373B2Test data compression method for system-on-chip using linear-feedback shift register reseedingNEC LAB AMERICA INC·Filed 2007·Granted Jun 1, 2010·3 cites·18 claims
- 1562US7577540B2Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boardsNEC CORP·Filed 2002·Granted Aug 18, 2009·8 cites·31 claims
- 1657US7818643B2Method for blocking unknown values in output response of scan test patterns for testing circuitsNEC LAB AMERICA INC·Filed 2008·Granted Oct 19, 2010·2 cites·12 claims
- 1756US7313743B2Hybrid scan-based delay testing technique for compact and high fault coverage test setNEC LAB AMERICA INC·Filed 2003·Granted Dec 25, 2007·7 cites·15 claims
- 1841US2010005041A1Machine learning based volume diagnosis of semiconductor chipsNEC LAB AMERICA INC·Filed 2008·Application pending·0 cites
- 1940US2008195904A1Test Point Insertion and Scan Chain Reordering for Broadcast-Scan Based CompressionNEC LAB AMERICA INC·Filed 2008·Application pending·0 cites
- 2039US2008091998A1Partial Enhanced Scan Method for Reducing Volume of Delay Test PatternsNEC LAB AMERICA INC·Filed 2007·Application pending·0 cites
- 2138US2007266283A1Method and Apparatus for Testing an Integrated CircuitNEC LAB AMERICA INC·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →