Inventor · disambiguated record
Prasenjit Biswas
Also filed as: BISWAS PRASENJIT
14 granted patents·1 pending application·119 citations·filing 1996–2021
91Inventor score
Files withHITACHI MICRO SYSTEMS INC3INTEL CORP3CADENCE DESIGN SYSTEMS INC2CHIU YI-JEN2HITACHI AMERICA LTD1
Top patents by PatentIndex Score
15 records- 0186US11797742B1Power aware real number modeling in dynamic verification of mixed-signal integrated circuit designSYNOPSYS INC·Filed 2021·Granted Oct 24, 2023·5 cites·20 claims
- 0286US8379723B2Chroma motion vector processing apparatus, system, and methodINTEL CORP·Filed 2006·Granted Feb 19, 2013·10 cites·21 claims
- 0384US8126046B2Flexible macroblock ordering and arbitrary slice ordering apparatus, system, and methodCHIU YI-JEN·Filed 2006·Granted Feb 28, 2012·7 cites·26 claims
- 0476US5860000AFloating point unit pipeline synchronized with processor pipelineHITACHI MICRO SYSTEMS INC·Filed 1996·Granted Jan 12, 1999·55 cites·8 claims
- 0575US7260792B2Modeling a mixed-language mixed-signal designCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Aug 21, 2007·9 cites·13 claims
- 0666US6772327B2Floating point unit pipeline synchronized with processor pipelineHITACHI MICRO SYSTEMS INC·Filed 2002·Granted Aug 3, 2004·8 cites·26 claims
- 0762US8630354B2Hardware accelerated compressed video bitstream escape code handlingJAHANGHIR MUSA·Filed 2006·Granted Jan 14, 2014·1 cites·6 claims
- 0862US7251795B2Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal designCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Jul 31, 2007·10 cites·18 claims
- 0958US9113151B2Hardware accelerated compressed video bitstream escape code handlingINTEL CORP·Filed 2013·Granted Aug 18, 2015·0 cites·11 claims
- 1056US7162616B2Floating point unit pipeline synchronized with processor pipelineRENESAS TECHNOLOGY AMERICA INC·Filed 2004·Granted Jan 9, 2007·3 cites·2 claims
- 1154US9313491B2Chroma motion vector processing apparatus, system, and methodINTEL CORP·Filed 2013·Granted Apr 12, 2016·0 cites·16 claims
- 1254US8644392B2Flexible macroblock ordering and arbitrary slice ordering apparatus, system, and methodCHIU YI-JEN·Filed 2012·Granted Feb 4, 2014·0 cites·20 claims
- 1343US2005262329A1Processor architecture for executing two different fixed-length instruction setsHITACHI LTD·Filed 2003·Application pending·0 cites
- 1439US6012139AMicroprocessor including floating point unit with 16-bit fixed length instruction setHITACHI MICRO SYSTEMS INC·Filed 1996·Granted Jan 4, 2000·10 cites·20 claims
- 1530US6418528B1Floating point unit pipeline synchronized with processor pipelineHITACHI AMERICA LTD·Filed 1998·Granted Jul 9, 2002·1 cites·8 claims
Join the waitlist — get patent alerts
Get an alert when Prasenjit Biswas files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →