Inventor · disambiguated record
Brian Foutz
Also filed as: FOUTZ BRIAN · Foutz Brian Edward
26 granted patents·252 citations·filing 2001–2022
96Inventor score
Top patents by PatentIndex Score
26 records- 0193US9606179B1Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializerCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 28, 2017·7 cites·18 claims
- 0290US9513335B1Method for using XOR trees for physically efficient scan compression and decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 6, 2016·5 cites·10 claims
- 0390US9470756B1Method for using sequential decompression logic for VLSI test in a physically efficient constructionCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·5 cites·20 claims
- 0488US7926012B1Design-For-testability plannerCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 12, 2011·26 cites·18 claims
- 0587US12007440B1Systems and methods for scan chain stitchingCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Jun 11, 2024·1 cites·20 claims
- 0687US11947887B1Test-point flop sharing with improved testability in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Apr 2, 2024·1 cites·20 claims
- 0787US9817068B1Method and system for improving efficiency of sequential test compression using overscanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·4 cites·12 claims
- 0887US8001433B1Scan testing architectures for power-shutoff aware systemsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Aug 16, 2011·15 cites·21 claims
- 0986US9470754B1Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serializationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·3 cites·20 claims
- 1085US10331506B1SoC top-level XOR compactor design to efficiently test and diagnose multiple identical coresCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 25, 2019·4 cites·17 claims
- 1185US7979764B2Distributed test compression for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jul 12, 2011·16 cites·21 claims
- 1282US10955470B1Method to improve testability using 2-dimensional exclusive or (XOR) gridsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 23, 2021·2 cites·9 claims
- 1382US10775435B1Low-power shift with clock staggeringCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 15, 2020·3 cites·12 claims
- 1482US6996515B1Enabling verification of a minimal level sensitive timing abstraction modelHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 7, 2006·37 cites·18 claims
- 1582US6604227B1Minimal level sensitive timing abstraction model capable of being used in general static timing analysis toolsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 5, 2003·37 cites·19 claims
- 1680US9817069B1Method and system for construction of a highly efficient and predictable sequential test decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·2 cites·20 claims
- 1780US6611948B1Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction modelHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 26, 2003·32 cites·19 claims
- 1877US10761131B1Method for optimally connecting scan segments in two-dimensional compression chainsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 1, 2020·2 cites·20 claims
- 1977US9470755B1Method for dividing testable logic into a two-dimensional grid for physically efficient scanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·2 cites·20 claims
- 2077US6581197B1Minimal level sensitive timing representative of a circuit pathHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jun 17, 2003·25 cites·20 claims
- 2176US6609233B1Load sensitivity modeling in a minimal level sensitive timing abstraction modelHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 19, 2003·23 cites·18 claims
- 2261US12307186B1Launch off shift processCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted May 20, 2025·0 cites·18 claims
- 2358US12412014B1IC chip with IC design modification detectionCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 9, 2025·0 cites·20 claims
- 2457US12475288B1Clock-based test-point flop sharing in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
- 2555US12511462B1Physical awareness of test-point sharing in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 30, 2025·0 cites·20 claims
- 2636US10551435B12D compression-based low power ATPGCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 4, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →