Inventor · disambiguated record
Sowmiya Jayachandran
Also filed as: JAYACHANDRAN SOWMIYA
11 granted patents·3 pending applications·35 citations·filing 2007–2019
88Inventor score
Top patents by PatentIndex Score
14 records- 0188US9202547B2Managing disturbance induced errorsINTEL CORP·Filed 2013·Granted Dec 1, 2015·8 cites·18 claims
- 0286US9916104B2Techniques for entry to a lower power state for a memory deviceINTEL CORP·Filed 2016·Granted Mar 13, 2018·4 cites·27 claims
- 0381US11036412B2Dynamically changing between latency-focused read operation and bandwidth-focused read operationINTEL CORP·Filed 2019·Granted Jun 15, 2021·3 cites·17 claims
- 0481US9818458B1Techniques for entry to a lower power state for a memory deviceINTEL CORP·Filed 2015·Granted Nov 14, 2017·5 cites·27 claims
- 0579US9778723B2Apparatuses and methods for exiting low power states in memory devicesMICRON TECHNOLOGY INC·Filed 2015·Granted Oct 3, 2017·2 cites·19 claims
- 0678US8001444B2ECC functional block placement in a multi-channel mass storage deviceINTEL CORP·Filed 2007·Granted Aug 16, 2011·3 cites·15 claims
- 0777US9417684B2Mechanism for facilitating power and performance management of non-volatile memory in computing devicesRAMAGE SIMON D·Filed 2011·Granted Aug 16, 2016·7 cites·12 claims
- 0873US10437307B2Apparatuses and methods for exiting low power states in memory devicesMICRON TECHNOLOGY INC·Filed 2017·Granted Oct 8, 2019·1 cites·19 claims
- 0971US9792963B2Managing disturbance induced errorsINTEL CORP·Filed 2015·Granted Oct 17, 2017·2 cites·22 claims
- 1064US11249531B2Apparatuses and methods for exiting low power states in memory devicesMICRON TECHNOLOGY INC·Filed 2019·Granted Feb 15, 2022·0 cites·20 claims
- 1150US10153015B2Managing disturbance induced errorsINTEL CORP·Filed 2017·Granted Dec 11, 2018·0 cites·28 claims
- 1244US2019278503A1Nvram memory module with hard write throttle downINTEL CORP·Filed 2019·Application pending·0 cites
- 1343US2009172213A1Command completion detection in a mass storage deviceJAYACHANDRAN SOWMIYA·Filed 2007·Application pending·0 cites
- 1439US2020133669A1Techniques for dynamic proximity based on-die terminationINTEL CORP·Filed 2019·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →