Inventor · disambiguated record
Sergio Camerlo
Also filed as: CAMERLO SERGIO · CAMERLO SERGIO D
14 granted patents·257 citations·filing 1998–2008
93Inventor score
Top patents by PatentIndex Score
14 records- 0194US7404250B2Method for fabricating a printed circuit board having a coaxial viaCISCO TECH INC·Filed 2005·Granted Jul 29, 2008·35 cites·13 claims
- 0294US6914780B1Methods and apparatus for cooling a circuit board component using a heat pipe assemblyCISCO TECH IND·Filed 2003·Granted Jul 5, 2005·87 cites·29 claims
- 0385US8035038B2Method for fabricating a printed circuit board having a coaxial viaCISCO TECH INC·Filed 2008·Granted Oct 11, 2011·13 cites·11 claims
- 0481US7154761B1Techniques for distributing current in a backplane assembly and methods for making the sameCISCO TECH INC·Filed 2004·Granted Dec 26, 2006·38 cites·15 claims
- 0570US7098408B1Techniques for mounting an area array package to a circuit board using an improved pad layoutCISCO TECH INC·Filed 2003·Granted Aug 29, 2006·18 cites·16 claims
- 0668US7053314B1Methods and apparatus for providing a signal to a circuit board componentCISCO TECH INC·Filed 2003·Granted May 30, 2006·15 cites·30 claims
- 0757US7574687B1Method and system to optimize timing margin in a system in package moduleCISCO TECH INC·Filed 2006·Granted Aug 11, 2009·1 cites·5 claims
- 0851US6069539AVTT power distribution systemCISCO TECH IND·Filed 1999·Granted May 30, 2000·28 cites·22 claims
- 0944US7185821B1Method and apparatus for delivering high-current power and ground voltages using top side of chip package substrateCISCO TECH INC·Filed 2003·Granted Mar 6, 2007·1 cites·35 claims
- 1041US6081106AVoltage setpoint error reductionCISCO TECH IND·Filed 1998·Granted Jun 27, 2000·7 cites·17 claims
- 1138US6204712B1Method and apparatus for clock uncertainty minimizationCISCO TECH IND·Filed 1999·Granted Mar 20, 2001·7 cites·2 claims
- 1236US6052012AMethod and apparatus for clock uncertainly minimizationCISCO TECH IND·Filed 1998·Granted Apr 18, 2000·4 cites·13 claims
- 1332US6157250AMethod and apparatus for clock uncertainty minimization with a clean power sourceCISCO TECH IND·Filed 1999·Granted Dec 5, 2000·2 cites·10 claims
- 1431US6157251AMethod and apparatus for clock uncertainty minimizationCISCO TECH IND·Filed 1999·Granted Dec 5, 2000·1 cites·12 claims
Join the waitlist — get patent alerts
Get an alert when Sergio Camerlo files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →