Inventor · disambiguated record
Sankerlingam Rajendran
Also filed as: RAJENDRAN SANKERLINGAM
14 granted patents·3 pending applications·118 citations·filing 1990–2021
90Inventor score
Top patents by PatentIndex Score
17 records- 0191US10096879B2Shaped magnetic bias circulatorRAYTHEON CO·Filed 2016·Granted Oct 9, 2018·4 cites·7 claims
- 0288US10573948B2Shaped magnetic bias circulatorRAYTHEON CO·Filed 2019·Granted Feb 25, 2020·2 cites·20 claims
- 0386US5102494AWet-tip die for EFG cyrstal growth apparatusMOBIL SOLAR ENERGY CORP·Filed 1991·Granted Apr 7, 1992·57 cites·3 claims
- 0479US7979144B2System for forming patterns on a multi-curved surfaceRAYTHEON CO·Filed 2008·Granted Jul 12, 2011·6 cites·24 claims
- 0577US10403958B2Method for making a composite substrate circulator componentRAYTHEON CO·Filed 2016·Granted Sep 3, 2019·2 cites·13 claims
- 0674US11096271B1Double-sided, high-density network fabricationRAYTHEON CO·Filed 2020·Granted Aug 17, 2021·1 cites·10 claims
- 0774US9899717B2Stacked low loss stripline circulatorRAYTHEON CO·Filed 2015·Granted Feb 20, 2018·2 cites·26 claims
- 0868US10727558B2Shaped magnetic bias circulatorRAYTHEON CO·Filed 2020·Granted Jul 28, 2020·0 cites·20 claims
- 0968US10431865B2Shaped magnetic bias circulatorRAYTHEON CO·Filed 2018·Granted Oct 1, 2019·0 cites·20 claims
- 1066US10356914B2Method of lamination of dielectric circuit materials using ultrasonic meansRAYTHEON CO·Filed 2016·Granted Jul 16, 2019·1 cites·18 claims
- 1165US11317505B2Double-sided, high-density network fabricationRAYTHEON CO·Filed 2021·Granted Apr 26, 2022·0 cites·20 claims
- 1264US5037622AWet-tip die for EFG crystal growth apparatusMOBIL SOLAR ENERGY CORP·Filed 1990·Granted Aug 6, 1991·17 cites·13 claims
- 1354US6583058B1Solid hermetic via and bump fabricationTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 24, 2003·25 cites·23 claims
- 1449US2019386371A1Method for Making a Composite Substrate Circulator ComponentRAYTHEON CO·Filed 2019·Application pending·0 cites
- 1549US2010300734A1Method and Apparatus for Building Multilayer CircuitsRAYTHEON CO·Filed 2009·Application pending·0 cites
- 1646US8963313B2Heterogeneous chip integration with low loss interconnection through adaptive patterningRAJENDRAN SANKERLINGAM·Filed 2011·Granted Feb 24, 2015·1 cites·39 claims
- 1741US2008099537A1Method for sealing vias in a substrateRAYTHEON CO·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →