Inventor · disambiguated record
Leendert M. Huisman
Also filed as: HUISMAN LEENDERT M · HUISMAN LEENDERT MARINUS
24 granted patents·1 pending application·451 citations·filing 1986–2007
97Inventor score
Files withIBM25
Top patents by PatentIndex Score
25 records- 0192US7139950B2Segmented scan chains with dynamic reconfigurationsIBM·Filed 2004·Granted Nov 21, 2006·58 cites·17 claims
- 0288US7240261B2Scan chain diagnostics using logic pathsIBM·Filed 2003·Granted Jul 3, 2007·19 cites·15 claims
- 0387US6519725B1Diagnosis of RAMS using functional patternsIBM·Filed 1997·Granted Feb 11, 2003·70 cites·15 claims
- 0483US6880136B2Method to detect systematic defects in VLSI manufacturingIBM·Filed 2002·Granted Apr 12, 2005·29 cites·22 claims
- 0582US7895487B2Scan chain diagnostics using logic pathsIBM·Filed 2007·Granted Feb 22, 2011·9 cites·16 claims
- 0682US6901542B2Internal cache for on chip test data storageIBM·Filed 2001·Granted May 31, 2005·35 cites·33 claims
- 0780US7194706B2Designing scan chains with specific parameter sensitivities to identify process defectsIBM·Filed 2004·Granted Mar 20, 2007·24 cites·26 claims
- 0879US6954916B2Methodology for fixing Qcrit at design timing impactIBM·Filed 2003·Granted Oct 11, 2005·26 cites·16 claims
- 0979US6865501B2Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collectionIBM·Filed 2003·Granted Mar 8, 2005·16 cites·7 claims
- 1079US6671644B2Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collectionIBM·Filed 2001·Granted Dec 30, 2003·15 cites·22 claims
- 1172US7752514B2Methods and apparatus for testing a scan chain to isolate defectsIBM·Filed 2007·Granted Jul 6, 2010·5 cites·8 claims
- 1272US6721914B2Diagnosis of combinational logic circuit failuresIBM·Filed 2001·Granted Apr 13, 2004·18 cites·12 claims
- 1371US6170078B1Fault simulation using dynamically alterable behavioral modelsIBM·Filed 1998·Granted Jan 2, 2001·36 cites·21 claims
- 1467US7434130B2Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collectionIBM·Filed 2004·Granted Oct 7, 2008·8 cites·3 claims
- 1567US7313744B2Methods and apparatus for testing a scan chain to isolate defectsIBM·Filed 2004·Granted Dec 25, 2007·10 cites·30 claims
- 1659US7558999B2Learning based logic diagnosisIBM·Filed 2004·Granted Jul 7, 2009·7 cites·17 claims
- 1758US6675323B2Incremental fault dictionaryIBM·Filed 2001·Granted Jan 6, 2004·8 cites·7 claims
- 1850US6785413B1Rapid defect analysis by placement of tester fail dataIBM·Filed 1999·Granted Aug 31, 2004·17 cites·20 claims
- 1946US7230335B2Inspection methods and structures for visualizing and/or detecting specific chip structuresIBM·Filed 2004·Granted Jun 12, 2007·1 cites·3 claims
- 2046US5297151AAdjustable weighted random test pattern generator for logic circuitsIBM·Filed 1992·Granted Mar 22, 1994·19 cites·16 claims
- 2145US2008098268A1Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collectionIBM·Filed 2007·Application pending·0 cites
- 2244US4726023ADetermination of testability of combined logic end memory by ignoring memoryIBM·Filed 1986·Granted Feb 16, 1988·8 cites·6 claims
- 2343US6931580B1Rapid fail analysis of embedded objectsIBM·Filed 2000·Granted Aug 16, 2005·6 cites·26 claims
- 2438US7089514B2Defect diagnosis for semiconductor integrated circuitsIBM·Filed 2004·Granted Aug 8, 2006·1 cites·20 claims
- 2536US6125461AMethod for identifying long paths in integrated circuitsIBM·Filed 1998·Granted Sep 26, 2000·6 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →