Inventor · disambiguated record
Mona A. Ebrish
Also filed as: EBRISH MONA · EBRISH MONA A · EBRISH MONA ABDULKHALEG
18 granted patents·1 pending application·446 citations·filing 2016–2024
91Inventor score
Top patents by PatentIndex Score
19 records- 0198US9799736B1High acceptor level doping in silicon germaniumIBM·Filed 2016·Granted Oct 24, 2017·420 cites·12 claims
- 0291US10811528B2Two step fin etch and reveal for VTFETs and high breakdown LDVTFETsIBM·Filed 2018·Granted Oct 20, 2020·7 cites·6 claims
- 0389US10734523B2Nanosheet substrate to source/drain isolationIBM·Filed 2018·Granted Aug 4, 2020·6 cites·20 claims
- 0489US10361306B2High acceptor level doping in silicon germaniumIBM·Filed 2017·Granted Jul 23, 2019·4 cites·6 claims
- 0588US9666486B1Contained punch through stopper for CMOS structures on a strain relaxed buffer substrateIBM·Filed 2016·Granted May 30, 2017·5 cites·20 claims
- 0684US9711507B1Separate N and P fin etching for reduced CMOS device leakageIBM·Filed 2016·Granted Jul 18, 2017·3 cites·14 claims
- 0772US11031250B2Semiconductor structures of more uniform thicknessIBM·Filed 2018·Granted Jun 8, 2021·1 cites·12 claims
- 0862US12476111B2Selective area diffusion doping of III-N materialsUS GOV SEC NAVY·Filed 2023·Granted Nov 18, 2025·0 cites·20 claims
- 0959US2024339367A1Erasable Nanocellulose ElectronicsUS GOV SEC NAVY·Filed 2024·Application pending·0 cites
- 1058US11043494B2Structure and method for equal substrate to channel height between N and P fin-FETsIBM·Filed 2019·Granted Jun 22, 2021·0 cites·19 claims
- 1156US10229910B2Separate N and P fin etching for reduced CMOS device leakageIBM·Filed 2017·Granted Mar 12, 2019·0 cites·20 claims
- 1255US10388789B2Reducing series resistance between source and/or drain regions and a channel regionIBM·Filed 2017·Granted Aug 20, 2019·0 cites·11 claims
- 1354US10319855B2Reducing series resistance between source and/or drain regions and a channel regionIBM·Filed 2017·Granted Jun 11, 2019·0 cites·9 claims
- 1452US10804106B2High temperature ultra-fast annealed soft mask for semiconductor devicesIBM·Filed 2018·Granted Oct 13, 2020·0 cites·18 claims
- 1551US10818751B2Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regionsIBM·Filed 2019·Granted Oct 27, 2020·0 cites·18 claims
- 1651US10381348B2Structure and method for equal substrate to channel height between N and P fin-FETsIBM·Filed 2017·Granted Aug 13, 2019·0 cites·18 claims
- 1750US12439653B2Multi-layer hybrid edge termination for III-N power devicesUS GOV SEC NAVY·Filed 2022·Granted Oct 7, 2025·0 cites·11 claims
- 1850US10361127B1Vertical transport FET with two or more gate lengthsIBM·Filed 2017·Granted Jul 23, 2019·0 cites·13 claims
- 1947US11569442B2Dielectric retention and method of forming memory pillarIBM·Filed 2020·Granted Jan 31, 2023·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →