Inventor · disambiguated record
Michael R. Trombley
Also filed as: TROMBLEY MICHAEL · TROMBLEY MICHAEL R · TROMBLEY MICHAEL RAYMOND
37 granted patents·9 pending applications·502 citations·filing 1992–2024
97Inventor score
Files withIBM23QUALCOMM INC5MICROSOFT TECHNOLOGY LICENSING LLC4BUCHMANN PETER2LASTRAS-MONTANO LUIS A2
Top patents by PatentIndex Score
46 records- 0195US10804919B1Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration systems and methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Oct 13, 2020·14 cites·22 claims
- 0293US8139430B2Power-on initialization and test for a cascade interconnect memory systemBUCHMANN PETER L·Filed 2008·Granted Mar 20, 2012·46 cites·19 claims
- 0392US9710324B2Dual in-line memory modules (DIMMs) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECCQUALCOMM INC·Filed 2015·Granted Jul 18, 2017·12 cites·30 claims
- 0491US6557053B1Queue manager for a bufferIBM·Filed 2000·Granted Apr 29, 2003·70 cites·12 claims
- 0589US8245105B2Cascade interconnect memory system with enhanced reliabilityDELL TIMOTHY J·Filed 2008·Granted Aug 14, 2012·21 cites·18 claims
- 0688US8516338B2Error correcting code protected quasi-static bit communication on a high-speed busBUCHMANN PETER·Filed 2012·Granted Aug 20, 2013·10 cites·25 claims
- 0786US7895502B2Error control coding methods for memories with subline accessesIBM·Filed 2007·Granted Feb 22, 2011·16 cites·20 claims
- 0881US10236917B2Providing memory bandwidth compression in chipkill-correct memory architecturesQUALCOMM INC·Filed 2016·Granted Mar 19, 2019·4 cites·24 claims
- 0980US6473838B1Data transfer system for multiple network processors using dual DRAM storageIBM·Filed 2000·Granted Oct 29, 2002·28 cites·15 claims
- 1079US9128868B2System for error decoding with retries and associated methodsLASTRAS-MONTANO LUIS A·Filed 2008·Granted Sep 8, 2015·9 cites·20 claims
- 1178US8099570B2Methods, systems, and computer program products for dynamic selective memory mirroringO'CONNOR JAMES A·Filed 2008·Granted Jan 17, 2012·10 cites·14 claims
- 1278US7937533B2Structure for handling data requestsIBM·Filed 2008·Granted May 3, 2011·9 cites·7 claims
- 1376US7944931B2Balanced bandwidth utilizationIBM·Filed 2007·Granted May 17, 2011·5 cites·26 claims
- 1475US8234540B2Error correcting code protected quasi-static bit communication on a high-speed busBUCHMANN PETER·Filed 2008·Granted Jul 31, 2012·8 cites·18 claims
- 1575US7286543B2Memory system with apparatus and method to enable balanced bandwidth utilizationIBM·Filed 2003·Granted Oct 23, 2007·17 cites·1 claims
- 1674US6601229B1Client/server behavioral modeling and testcase development using VHDL for improved logic verificationIBM·Filed 2000·Granted Jul 29, 2003·24 cites·11 claims
- 1772US5471626AVariable stage entry/exit instruction pipelineIBM·Filed 1992·Granted Nov 28, 1995·59 cites·17 claims
- 1871US8547760B2Memory access alignment in a double data rate (‘DDR’) systemJENKINS STEVEN K·Filed 2011·Granted Oct 1, 2013·4 cites·8 claims
- 1971US8140825B2Systems and methods for selectively closing pages in a memoryBALAKRISHNAN GANESH·Filed 2008·Granted Mar 20, 2012·5 cites·20 claims
- 2071US7949830B2System and method for handling data requestsIBM·Filed 2007·Granted May 24, 2011·5 cites·11 claims
- 2170US8122216B2Systems and methods for masking latency of memory reorganization work in a compressed memory systemDALY DAVID MICHAEL·Filed 2006·Granted Feb 21, 2012·7 cites·25 claims
- 2269US8181094B2System to improve error correction using variable latency and associated methodsLASTRAS-MONTANO LUIS A·Filed 2008·Granted May 15, 2012·4 cites·20 claims
- 2369US8028257B2Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency modeIBM·Filed 2008·Granted Sep 27, 2011·4 cites·15 claims
- 2465US6584518B1Cycle saving technique for managing linked listsIBM·Filed 2000·Granted Jun 24, 2003·10 cites·23 claims
- 2564US5781763AIndependent control of DMA and I/O resources for mixed-endian computing systemsIBM·Filed 1997·Granted Jul 14, 1998·45 cites·9 claims
- 2663US2025378040A1Ungrouping and grouping of system busses using link macros capable of joining and splittingMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2024·Application pending·0 cites
- 2762US6766381B1VLSI network processor and methodsIBM·Filed 1999·Granted Jul 20, 2004·48 cites·17 claims
- 2861US8176391B2System to improve miscorrection rates in error control code through buffering and associated methodsBAYSAH IRVING G·Filed 2008·Granted May 8, 2012·3 cites·20 claims
- 2961US7657771B2Method and apparatus for reducing latency associated with read operations in a memory systemIBM·Filed 2007·Granted Feb 2, 2010·2 cites·19 claims
- 3061US2025378039A1Multi-die systems with modular die-to-die link macros for enabling die-to-die communicationMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2024·Application pending·0 cites
- 3160US8902683B2Memory access alignment in a double data rate (‘DDR’) systemIBM·Filed 2013·Granted Dec 2, 2014·1 cites·8 claims
- 3258US8032713B2Structure for handling data accessIBM·Filed 2008·Granted Oct 4, 2011·1 cites·20 claims
- 3358US7660952B2Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency modeIBM·Filed 2007·Granted Feb 9, 2010·1 cites·20 claims
- 3451US11838153B1Digital signal processors providing scalable decision feedback equalization (DFE) employing sequence selection and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Dec 5, 2023·0 cites·20 claims
- 3550US9343123B2Memory access alignment in a double data rate (‘DDR’) systemIBM·Filed 2014·Granted May 17, 2016·0 cites·6 claims
- 3649US10411873B1Clock data recovery broadcast for multi-lane SerDesQUALCOMM INC·Filed 2018·Granted Sep 10, 2019·0 cites·12 claims
- 3748US9436388B2Memory access alignment in a double data rate (‘DDR’) systemIBM·Filed 2016·Granted Sep 6, 2016·0 cites·11 claims
- 3848US9053031B2System and method for handling data accessALLEN JR JAMES JOHNSON·Filed 2007·Granted Jun 9, 2015·0 cites·15 claims
- 3948US8140803B2Structure for reducing latency associated with read operations in a memory systemALLEN JR JAMES J·Filed 2008·Granted Mar 20, 2012·0 cites·20 claims
- 4048US2010005212A1Providing a variable frame format protocol in a cascade interconnected memory systemIBM·Filed 2008·Application pending·0 cites
- 4147US2010005206A1Automatic read data flow control in a cascade interconnect memory systemIBM·Filed 2008·Application pending·0 cites
- 4247US2009276559A1Arrangements for Operating In-Line Memory Module ConfigurationsIBM·Filed 2008·Application pending·0 cites
- 4346US2010005214A1Enhancing bus efficiency in a memory systemIBM·Filed 2008·Application pending·0 cites
- 4443US2008098176A1Method and Apparatus for Implementing Memory Accesses Using Open Page Mode for Data PrefetchingKRISHNA M V V ANIL·Filed 2006·Application pending·0 cites
- 4538US2019087351A1Transaction dispatcher for memory management unitQUALCOMM INC·Filed 2018·Application pending·0 cites
- 4637US2016224241A1PROVIDING MEMORY BANDWIDTH COMPRESSION USING BACK-TO-BACK READ OPERATIONS BY COMPRESSED MEMORY CONTROLLERS (CMCs) IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEMQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →