Inventor · disambiguated record
Jack Hwang
Also filed as: HWANG JACK · HWANG JACK CHANKOU
27 granted patents·16 pending applications·376 citations·filing 2001–2025
97Inventor score
Top patents by PatentIndex Score
43 records- 0198US11887891B2Self-aligned contactsINTEL CORP·Filed 2023·Granted Jan 30, 2024·2 cites·20 claims
- 0298US8436404B2Self-aligned contactsBOHR MARK T·Filed 2009·Granted May 7, 2013·148 cites·30 claims
- 0397US9508821B2Self-aligned contactsINTEL CORP·Filed 2015·Granted Nov 29, 2016·13 cites·3 claims
- 0497US9466565B2Self-aligned contactsINTEL CORP·Filed 2015·Granted Oct 11, 2016·24 cites·18 claims
- 0597US9054178B2Self-aligned contactsBOHR MARK T·Filed 2014·Granted Jun 9, 2015·30 cites·12 claims
- 0695US9093513B2Self-aligned contactsBOHR MARK T·Filed 2013·Granted Jul 28, 2015·12 cites·14 claims
- 0791US10930557B2Self-aligned contactsINTEL CORP·Filed 2020·Granted Feb 23, 2021·2 cites·12 claims
- 0887US12266571B2Self-aligned contactsINTEL CORP·Filed 2023·Granted Apr 1, 2025·0 cites·16 claims
- 0986US10141226B2Self-aligned contactsINTEL CORP·Filed 2017·Granted Nov 27, 2018·2 cites·27 claims
- 1086US6638802B1Forming strained source drain junction field effect transistorsINTEL CORP·Filed 2002·Granted Oct 28, 2003·35 cites·18 claims
- 1182US2025239486A1Self-aligned contactsINTEL CORP·Filed 2025·Application pending·0 cites
- 1281US7439113B2Forming dual metal complementary metal oxide semiconductor integrated circuitsINTEL CORP·Filed 2004·Granted Oct 21, 2008·23 cites·7 claims
- 1376US11600524B2Self-aligned contactsINTEL CORP·Filed 2021·Granted Mar 7, 2023·0 cites·12 claims
- 1476US7758238B2Temperature measurement with reduced extraneous infrared in a processing chamberINTEL CORP·Filed 2008·Granted Jul 20, 2010·8 cites·15 claims
- 1576US7102141B2Flash lamp annealing apparatus to generate electromagnetic radiation having selective wavelengthsINTEL CORP·Filed 2004·Granted Sep 5, 2006·19 cites·26 claims
- 1673US7109443B2Multi-zone reflecting device for use in flash lamp processesINTEL CORP·Filed 2004·Granted Sep 19, 2006·16 cites·26 claims
- 1772US7892971B2Sub-second annealing processes for semiconductor devicesINTEL CORP·Filed 2008·Granted Feb 22, 2011·5 cites·15 claims
- 1871US7223660B2Flash assisted annealingINTEL CORP·Filed 2002·Granted May 29, 2007·13 cites·6 claims
- 1967US10629483B2Self-aligned contactsINTEL CORP·Filed 2018·Granted Apr 21, 2020·0 cites·20 claims
- 2067US6936518B2Creating shallow junction transistorsINTEL CORP·Filed 2004·Granted Aug 30, 2005·8 cites·14 claims
- 2163US7479431B2Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drainINTEL CORP·Filed 2004·Granted Jan 20, 2009·6 cites·18 claims
- 2262US9892967B2Self-aligned contactsINTEL CORP·Filed 2016·Granted Feb 13, 2018·0 cites·8 claims
- 2359US2025201768A1Package architectures having vertically stacked dies with high capacity memory for power deliveryINTEL CORP·Filed 2023·Application pending·0 cites
- 2459US2025201793A1Package architectures having vertically stacked dies for high capacity memoryINTEL CORP·Filed 2023·Application pending·0 cites
- 2558US7858981B2Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drainINTEL CORP·Filed 2009·Granted Dec 28, 2010·0 cites·26 claims
- 2658US2025201766A1Package architectures having vertically stacked dies and voltage convertersINTEL CORP·Filed 2023·Application pending·0 cites
- 2758US2025210587A1Package architectures having vertically stacked dies and voltage domain stackingINTEL CORP·Filed 2023·Application pending·0 cites
- 2855US6808993B2Ultra-thin gate dielectricsINTEL CORP·Filed 2003·Granted Oct 26, 2004·8 cites·22 claims
- 2950US2009020825A1Forming dual metal complementary metal oxide semiconductor integrated circuitsDOCZY MARK·Filed 2008·Application pending·0 cites
- 3049US2011147804A1Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantationMEHANDRU RISHABH·Filed 2009·Application pending·0 cites
- 3148US6911706B2Forming strained source drain junction field effect transistorsINTEL CORP·Filed 2003·Granted Jun 28, 2005·2 cites·5 claims
- 3248US2005191834A1Creating shallow junction transistorsFiled 2005·Application pending·0 cites
- 3345US8426858B2Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drainHATTENDORF MICHAEL L·Filed 2010·Granted Apr 23, 2013·0 cites·20 claims
- 3442US7790587B2Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed therebyINTEL CORP·Filed 2006·Granted Sep 7, 2010·0 cites·8 claims
- 3542US6462238B2Process for the reduction of cyano-substituted sulfones to aminoalkylene-substituted sulfonesARRAY BIOPHARMA INC·Filed 2001·Granted Oct 8, 2002·0 cites·16 claims
- 3642US2008242117A1Apparatus to reduce wafer edge temperature and breakage of wafersRAMANARAYANAN PANCHAPAKESAN·Filed 2007·Application pending·0 cites
- 3741US2011147831A1Method for replacement metal gate fillSTEIGERWALD JOSEPH M·Filed 2009·Application pending·0 cites
- 3836US2004102013A1Codoping of source drains using carbon or fluorine ion implants to improve polysilicon depletionFiled 2002·Application pending·0 cites
- 3936US2002197885A1Method of making a semiconductor transistor by implanting ions into a gate dielectric layer thereofFiled 2001·Application pending·0 cites
- 4035US2006286807A1Use of active temperature control to provide emmisivity independent wafer temperatureHWANG JACK·Filed 2005·Application pending·0 cites
- 4132US2007099404A1Implant and anneal amorphization processGOVINDARAJU SRIDHAR·Filed 2005·Application pending·0 cites
- 4232US2006004493A1Use of active temperature control to provide emmisivity independent wafer temperatureHWANG JACK·Filed 2004·Application pending·0 cites
- 4329US2013208729A1Systems and methods for facilitation of communications sessions amongst a plurality of networksNEUTRAL TANDEM INC D B A INTELIQUENT·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →