Inventor · disambiguated record
Hiroyuki Tsujikawa
Also filed as: TSUJIKAWA HIROYUKI
19 granted patents·10 pending applications·325 citations·filing 1999–2007
95Inventor score
Top patents by PatentIndex Score
29 records- 0187US6434730B1Pattern forming methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2000·Granted Aug 13, 2002·68 cites·8 claims
- 0280US7062732B2Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Jun 13, 2006·30 cites·21 claims
- 0376US7171645B2Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Jan 30, 2007·22 cites·18 claims
- 0476US6710449B2Interconnection structure and method for designing the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2002·Granted Mar 23, 2004·25 cites·7 claims
- 0575US6303251B1Mask pattern correction process, photomask and semiconductor integrated circuit deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1999·Granted Oct 16, 2001·37 cites·12 claims
- 0673US6782347B2Method for optimizing electromagnetic interference and method for analyzing the electromagnetic interferenceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2001·Granted Aug 24, 2004·20 cites·27 claims
- 0772US7039572B1Method of analyzing electromagnetic interferenceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2000·Granted May 2, 2006·27 cites·2 claims
- 0872US6810340B2Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2002·Granted Oct 26, 2004·19 cites·58 claims
- 0968US6876210B2Method and apparatus for analyzing electromagnetic interferenceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2001·Granted Apr 5, 2005·14 cites·28 claims
- 1066US7278124B2Design method for semiconductor integrated circuit suppressing power supply noiseMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2004·Granted Oct 2, 2007·13 cites·22 claims
- 1162US6754598B2Electromagnetic interference analysis method and apparatusMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2002·Granted Jun 22, 2004·10 cites·50 claims
- 1261US6959250B1Method of analyzing electromagnetic interferenceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2000·Granted Oct 25, 2005·10 cites·11 claims
- 1360US7114144B2Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Sep 26, 2006·7 cites·19 claims
- 1460US6490709B1Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized regionMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2000·Granted Dec 3, 2002·6 cites·26 claims
- 1556US7307333B2Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2002·Granted Dec 11, 2007·6 cites·9 claims
- 1655US7911027B2Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor devicePANASONIC CORP·Filed 2007·Granted Mar 22, 2011·1 cites·6 claims
- 1753US6943129B2Interconnection structure and method for designing the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Sep 13, 2005·6 cites·6 claims
- 1850US2007136702A1Semiconductor device layout inspection methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2007·Application pending·0 cites
- 1950US2007009147A1Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2006·Application pending·0 cites
- 2046US6718528B2Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized regionMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2002·Granted Apr 6, 2004·0 cites·27 claims
- 2146US2004139407A1Semiconductor device layout inspection methodMUKAI KIYOHITO·Filed 2003·Application pending·0 cites
- 2244US2005005254A1Substrate noise analyzing method for semiconductor integrated circuit, semiconductor integrated circuit, and substrate noise analyzing device for semiconductor integrated circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2004·Application pending·0 cites
- 2343US2006091550A1Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2005·Application pending·0 cites
- 2440US2005224914A1Semiconductor integrated circuit device, method of enerating pattern thereof, method of manufacturing the same, and pattern generating apparatus for the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2005·Application pending·0 cites
- 2536US6183920B1Semiconductor device geometrical pattern correction process and geometrical pattern extraction processMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1999·Granted Feb 6, 2001·4 cites·21 claims
- 2636US2005204327A1Layout data verification method, mask pattern verification method and circuit operation verification methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2005·Application pending·0 cites
- 2734US2005114054A1Method for analyzing power supply noise of semiconductor integrated circuitFiled 2004·Application pending·0 cites
- 2834US2002109205A1Semiconductor device, method of creating pattern of the same, method of manufacturing the same, and apparatus for creating pattern of the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2002·Application pending·0 cites
- 2933US2002045995A1Electromagnetic interference analysis method and apparatusFiled 2001·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Hiroyuki Tsujikawa files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →