Inventor · disambiguated record
Bruce Gieseke
Also filed as: GIESEKE BRUCE · GIESEKE BRUCE A · GIESEKE BRUCE ALAN
20 granted patents·3 pending applications·419 citations·filing 1990–2014
96Inventor score
Files withADVANCED MICRO DEVICES INC5DIGITAL EQUIPMENT CORP5HEWLETT PACKARD DEVELOPMENT CO4COMPAQ COMPUTER CORP3COMPAQ INFORMATION TECHNOLOGIE1
Top patents by PatentIndex Score
23 records- 0191US5890201AContent addressable memory having memory cells storing don't care states for address translationDIGITAL EQUIPMENT CORP·Filed 1997·Granted Mar 30, 1999·75 cites·4 claims
- 0284US5023480APush-pull cascode logicDIGITAL EQUIPMENT CORP·Filed 1990·Granted Jun 11, 1991·47 cites·18 claims
- 0383US5568415AContent addressable memory having a pair of memory cells storing don't care states for address translationDIGITAL EQUIPMENT CORP·Filed 1993·Granted Oct 22, 1996·41 cites·7 claims
- 0481US7062850B2Method of forming electrical interconnects having electromigration-inhibiting segments to a critical lengthHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jun 20, 2006·24 cites·15 claims
- 0579US6363471B1Mechanism for handling 16-bit addressing in a processorADVANCED MICRO DEVICES INC·Filed 2000·Granted Mar 26, 2002·28 cites·38 claims
- 0674US6678951B2Method of forming electrical interconnects having electromigration-inhibiting plugsHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Jan 20, 2004·15 cites·4 claims
- 0771US6675288B2Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 6, 2004·16 cites·16 claims
- 0869US6245996B1Electrical interconnect structure having electromigration-inhibiting segmentsCOMPAQ COMPUTER CORP·Filed 1999·Granted Jun 12, 2001·30 cites·12 claims
- 0965US6904675B1Method of forming electrical interconnects having electromigration-inhibiting plugsHEWLETT PACKARD DEVELOPMENT LP·Filed 2003·Granted Jun 14, 2005·11 cites·20 claims
- 1061US6167508ARegister scoreboard logic with register read availability signal to reduce instruction issue arbitration latencyCOMPAQ COMPUTER CORP·Filed 1998·Granted Dec 26, 2000·38 cites·22 claims
- 1158US5784709ATranslating buffer and method for translating addresses utilizing invalid and don't care statesDIGITAL EQUIPMENT CORP·Filed 1996·Granted Jul 21, 1998·27 cites·4 claims
- 1253US8848479B2Multiple write during simultaneous memory access of a multi-port memory deviceNGU HUI H·Filed 2011·Granted Sep 30, 2014·2 cites·13 claims
- 1352US6807107B1Semiconductor memory with shadow memory cellADVANCED MICRO DEVICES INC·Filed 2002·Granted Oct 19, 2004·7 cites·20 claims
- 1452US6433389B1Silicon on insulator logic circuit utilizing diode switching elementsADVANCED MICRO DEVICES INC·Filed 2000·Granted Aug 13, 2002·5 cites·13 claims
- 1549US6249855B1Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycleCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 19, 2001·21 cites·48 claims
- 1646US2004098566A1Method and apparatus for compacting a queueFiled 2003·Application pending·0 cites
- 1744USRE46474EMultiple write during simultaneous memory access of a multi-port memory deviceEASIC CORP·Filed 2014·Granted Jul 11, 2017·0 cites·13 claims
- 1843US6704856B1Method for compacting an instruction queueHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Mar 9, 2004·14 cites·2 claims
- 1940US6405304B1Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Jun 11, 2002·12 cites·8 claims
- 2036US6798712B2Wordline latching in semiconductor memoriesADVANCED MICRO DEVICES INC·Filed 2002·Granted Sep 28, 2004·1 cites·22 claims
- 2136US6195377B1Embedded input logic in a high input impedance strobed CMOS differential sense amplifierDIGITAL EQUIPMENT CORP·Filed 1999·Granted Feb 27, 2001·5 cites·55 claims
- 2235US2012105129A1Apparatus for monolithic power gating on an integrated circuitNAFFZIGER SAMUEL D·Filed 2010·Application pending·0 cites
- 2335US2005167733A1Memory device and method of manufactureADVANCED MICRO DEVICES INC·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →