Inventor · disambiguated record
Chakrapani Pathikonda
Also filed as: PATHIKONDA CHAKRAPANI
10 granted patents·352 citations·filing 1996–2000
91Inventor score
Files withINTEL CORP10
Top patents by PatentIndex Score
10 records- 0194US6208180B1Core clock correction in a 2/N mode clocking schemeINTEL CORP·Filed 1998·Granted Mar 27, 2001·181 cites·15 claims
- 0283US6268749B1Core clock correction in a 2/n mode clocking schemeINTEL CORP·Filed 2000·Granted Jul 31, 2001·28 cites·21 claims
- 0363US6061599AAuto-configuration support for multiple processor-ready pair or FRC-master/checker pairINTEL CORP·Filed 1996·Granted May 9, 2000·31 cites·36 claims
- 0461US5802132AApparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking schemeINTEL CORP·Filed 1996·Granted Sep 1, 1998·33 cites·22 claims
- 0556US5862373APad cells for a 2/N mode clocking schemeINTEL CORP·Filed 1996·Granted Jan 19, 1999·36 cites·23 claims
- 0643US6104219AMethod and apparatus for generating 2/N mode bus clock signalsINTEL CORP·Filed 1998·Granted Aug 15, 2000·13 cites·17 claims
- 0742US5834956ACore clock correction in a 2/N mode clocking schemeINTEL CORP·Filed 1996·Granted Nov 10, 1998·11 cites·12 claims
- 0840US6114887AApparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking schemeINTEL CORP·Filed 1997·Granted Sep 5, 2000·10 cites·24 claims
- 0937US5826067AMethod and apparatus for preventing logic glitches in a 2/n clocking schemeINTEL CORP·Filed 1996·Granted Oct 20, 1998·9 cites·19 claims
- 1030US5821784AMethod and apparatus for generating 2/N mode bus clock signalsINTEL CORP·Filed 1996·Granted Oct 13, 1998·0 cites·42 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →